From: Luke Kenneth Casson Leighton Date: Sun, 15 Apr 2018 01:00:26 +0000 (+0100) Subject: att ZOLC link X-Git-Tag: convert-csv-opcode-to-binary~5673 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cab76ba12bc3b4175b59268074861b2766ee440b;p=libreriscv.git att ZOLC link --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index fa576aa7e..1fccd9e5b 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -265,14 +265,15 @@ contains an extremely interesting feature: zero-overhead loops. This proposal would basically allow an inner loop of instructions to be repeated indefinitely, a fixed number of times. -Its specific advantage over explicit loops is that the pipeline in a -DSP can potentially be kept completely full *even in an in-order +Its specific advantage over explicit loops is that the pipeline in a DSP +can potentially be kept completely full *even in an in-order single-issue implementation*. Normally, it requires a superscalar architecture and -out-of-order execution capabilities to "pre-process" instructions in order -to keep ALU pipelines 100% occupied. +out-of-order execution capabilities to "pre-process" instructions in +order to keep ALU pipelines 100% occupied. -This very simple proposal offers a way to increase pipeline activity in the -one key area which really matters: the inner loop. +By bringing that capability in, this proposal offers a way to increase +pipeline activity even in simpler implementations in the one key area +which really matters: the inner loop. ## Mask and Tagging (Predication) @@ -1234,3 +1235,4 @@ pluses: * Videocore-IV * Discussion proposing CSRs that change ISA definition +* Zero-overhead loops