From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 24 Apr 2022 14:57:11 +0000 (+0100)
Subject: add RESET_ADDRESS parameter into Makefile,
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cac26c0b5e37c7c6843ba26634c4002be05417f8;p=microwatt.git

add RESET_ADDRESS parameter into Makefile,
bring it into top-generic.vhdl, but shifted by 16 because VHDL refuses
to allow 32-bit integers (only 31-bit, sigh)
---

diff --git a/Makefile b/Makefile
index c6e31d4..610f48d 100644
--- a/Makefile
+++ b/Makefile
@@ -214,7 +214,10 @@ _fpga_files = fpga/soc_reset.vhdl \
 	nonrandom.vhdl
 
 # use an alternative core (in verilog)
-EXTERNAL_CORE=true
+EXTERNAL_CORE=false
+# VHDL does not allow integers greater than 2^32, so shift down
+# by 16 bits and add 16 bits zeros back on in soc-generic.vhdl
+RESET_ADDRESS=65280 # 0xff00_0000>>16
 ifeq ($(EXTERNAL_CORE),false)
     fpga_files = $(_fpga_files) $(_soc_files) $(core_files)
     synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
@@ -226,9 +229,14 @@ else
     soc_extra_v = external_core_top.v
 endif
 
-GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
-	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) \
-	-gSIM_MAIN_BRAM=$(SIM_MAIN_BRAM) -gSIM_BRAM_CHAINBOOT=$(SIM_BRAM_CHAINBOOT) \
+GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) \
+    -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
+	-gRESET_LOW=$(RESET_LOW) \
+	-gRESET_ADDRESS=$(RESET_ADDRESS) \
+    -gCLK_INPUT=$(CLK_INPUT) \
+    -gCLK_FREQUENCY=$(CLK_FREQUENCY) \
+	-gSIM_MAIN_BRAM=$(SIM_MAIN_BRAM) \
+    -gSIM_BRAM_CHAINBOOT=$(SIM_BRAM_CHAINBOOT) \
 	-gEXTERNAL_CORE=$(EXTERNAL_CORE)
 
 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 3aabe93..0ce8456 100644
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -1,5 +1,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 library work;
 use work.wishbone_types.all;
@@ -14,6 +15,7 @@ entity toplevel is
 	EXTERNAL_CORE     : boolean  := false;
 	SIM_MAIN_BRAM     : boolean  := false;
 	SIM_BRAM_CHAINBOOT  : positive  := 0;
+	RESET_ADDRESS  : integer  := 0;
 	CLK_INPUT     : positive := 100000000;
 	CLK_FREQUENCY : positive := 100000000;
         HAS_FPU       : boolean  := true;
@@ -102,7 +104,9 @@ begin
             LOG_LENGTH    => LOG_LENGTH,
 	    DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
             UART0_IS_16550     => UART_IS_16550,
-            HAS_UART1     => HAS_UART1
+            HAS_UART1     => HAS_UART1,
+            RESET_ADDRESS => (std_ulogic_vector(to_unsigned(RESET_ADDRESS, 48)
+                              & x"0000"))
 	    )
 	port map (
 	    system_clk        => system_clk,