From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Aug 2016 12:26:33 +0000 (+0200)
Subject: Fixed bug in memory_share for memory ports with different ABITS
X-Git-Tag: yosys-0.7~113
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cad40fc87449e69a086a627bfb25aa49ae400753;p=yosys.git

Fixed bug in memory_share for memory ports with different ABITS
---

diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index f298169de..bcb7433a2 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -619,6 +619,12 @@ struct MemoryShareWorker
 
 			RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
 
+			if (GetSize(last_addr) < GetSize(this_addr))
+				last_addr.extend_u0(GetSize(this_addr));
+			else
+				this_addr.extend_u0(GetSize(last_addr));
+
+			wr_ports[i]->setParam("\\ABITS", GetSize(this_addr));
 			wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
 			wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));