From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Aug 2014 08:37:47 +0000 (+0200)
Subject: Added multi-dim memory test (requires iverilog git head)
X-Git-Tag: yosys-0.4~281
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cad98bcd89cd9747f3ea9e35eed8d9bbedd64d7a;p=yosys.git

Added multi-dim memory test (requires iverilog git head)
---

diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index 9fed1bf3b..db06c56d2 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -194,3 +194,14 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+// ----------------------------------------------------------
+
+module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y);
+	reg [3:0] mem [0:15] [0:15];
+	always @(posedge clk) begin
+		y <= mem[a][b];
+		mem[a][b] <= c;
+	end
+endmodule
+