From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sun, 5 May 2013 10:58:24 +0000 (+0200)
Subject: dvisampler/chansync: fix FIFO width
X-Git-Tag: 24jan2021_ls180~2956
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb008a061cea67599ce3710bf5aaa0eeb9706015;p=litex.git

dvisampler/chansync: fix FIFO width
---

diff --git a/milkymist/dvisampler/chansync.py b/milkymist/dvisampler/chansync.py
index 5f53de18..95dd6802 100644
--- a/milkymist/dvisampler/chansync.py
+++ b/milkymist/dvisampler/chansync.py
@@ -2,7 +2,7 @@ from migen.fhdl.structure import *
 from migen.fhdl.module import Module
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fifo import SyncFIFO
-from migen.genlib.record import Record
+from migen.genlib.record import Record, layout_len
 from migen.genlib.misc import optree
 from migen.bank.description import *
 
@@ -27,7 +27,7 @@ class ChanSync(Module, AutoCSR):
 
 			###
 		
-			fifo = SyncFIFO(10, depth)
+			fifo = SyncFIFO(layout_len(channel_layout), depth)
 			self.add_submodule(fifo, "pix")
 			self.comb += [
 				fifo.we.eq(self.valid_i),