From: Luke Kenneth Casson Leighton Date: Thu, 21 Feb 2019 00:18:18 +0000 (+0000) Subject: whitespace cleanup X-Git-Tag: div_pipeline~2390 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb091a10e1839d0659fb9486525eb71a589d5763;p=soc.git whitespace cleanup --- diff --git a/TLB/CAM.py b/TLB/CAM.py index 7016eb01..694925b2 100644 --- a/TLB/CAM.py +++ b/TLB/CAM.py @@ -12,22 +12,22 @@ class CAM(): entry_array = Array(CamEntry(key_size, data_size) \ for x in range(cam_size)) encoder_input = Signal(cam_size) - + # Input self.write = Signal(1) # Denotes read (0) or write (1) self.address = Signal(max=cam_size) # address of the CAM to be written self.key = Signal(key_size) # The key to search for or to be written self.data_in = Signal(key_size) # The data to be written - + # Output self.data_hit = Signal(1) # Denotes a key data pair was stored at key_in self.data_out = Signal(data_size) # The data mapped to by key_in - + def elaborate(self, platform): m = Module() - + m.d.submodules.encoder = encoder = Encoder(cam_size) - + # Set the key value for every CamEntry for index in range(cam_size): m.d.sync += [ @@ -38,8 +38,7 @@ class CAM(): encoder_input[index].eq(entry_array[index].match) ) ] - - + m.d.sync += [ encoder.i.eq(encoder_input), # 1. Read request @@ -48,15 +47,15 @@ class CAM(): # 0 denotes a mapping was found If(encoder.n == 0, self.data_hit.eq(0), - self.data_out.eq(entry_array[encoder.o].data) + self.data_out.eq(entry_array[encoder.o].data) ).Else( - self.data_hit.eq(1) + self.data_hit.eq(1) ) ).Else( entry_array[self.address].key_in.eq(self.key_in), entry_array[self.address].data.eq(self.data_in) ) - + ] - + return m