From: lkcl <lkcl@web>
Date: Mon, 14 Dec 2020 00:21:29 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1333
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb1a2703d32e804af17e93dcc3ccca26132233fa;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 758296263..6c0646eb1 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -208,6 +208,7 @@ Standard PowerISA floating-point and VSX registers are aliased to some of the SV
 When vectorized, the CR inputs/outputs are read/written to 4-bit CR fields
 starting from CR6 and incrementing from there. If CR63 is reached, the next CR
 field used wraps around to CR0, then incrementing from there.
+(see [[discussion]].  an alternative scheme is described there)
 
 CR6 was chosen to balance avoiding needing to save CR2-CR4 (which are
 callee-saved) just to use SV vectors with VL <= 61 as well as having the first