From: whitequark <whitequark@whitequark.org>
Date: Sun, 27 Dec 2020 05:00:04 +0000 (+0000)
Subject: CODEOWNERS: add @zachjs as Verilog/AST frontend owner
X-Git-Tag: working-ls180~143^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb2283389df6fbd2f6aa8393e8d1960123ec72f4;p=yosys.git

CODEOWNERS: add @zachjs as Verilog/AST frontend owner
---

diff --git a/CODEOWNERS b/CODEOWNERS
index 350a62120..0419e6e44 100644
--- a/CODEOWNERS
+++ b/CODEOWNERS
@@ -25,6 +25,9 @@ passes/opt/opt_lut.cc          @whitequark
 # These still override previous lines, so be careful not to
 # accidentally disable any of the above rules.
 
+frontends/verilog/             @zachjs
+frontends/ast/                 @zachjs
+
 techlibs/intel_alm/            @ZirconiumX
 
 # pyosys