From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 28 May 2019 13:33:47 +0000 (+0200)
Subject: Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
X-Git-Tag: yosys-0.9~101^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb285e4b87112779efe84a7b6c5ae4a76a69ae01;p=yosys.git

Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg
index fe861b728..6adab4e5f 100644
--- a/passes/pmgen/peepopt_shiftmul.pmg
+++ b/passes/pmgen/peepopt_shiftmul.pmg
@@ -1,4 +1,7 @@
 pattern shiftmul
+//
+// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
+//
 
 state <SigSpec> shamt
 
@@ -49,12 +52,16 @@ code
 	if (GetSize(port(shift, \Y)) > const_factor)
 		reject;
 
+	int factor_bits = ceil_log2(const_factor);
+	SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
+
+	if (GetSize(shamt) < factor_bits+GetSize(mul_din))
+		reject;
+
 	did_something = true;
 	log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
 
-	int new_const_factor_log2 = ceil_log2(const_factor);
-	int new_const_factor = 1 << new_const_factor_log2;
-
+	int new_const_factor = 1 << factor_bits;
 	SigSpec padding(State::Sx, new_const_factor-const_factor);
 	SigSpec old_a = port(shift, \A), new_a;
 	int trunc = 0;
@@ -73,7 +80,7 @@ code
 	if (trunc > 0)
 		new_a.remove(GetSize(new_a)-trunc, trunc);
 
-	SigSpec new_b = {port(mul, const_factor_port == \A ? \B : \A), SigSpec(State::S0, new_const_factor_log2)};
+	SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
 	if (param(shift, \B_SIGNED).as_bool())
 		new_b.append(State::S0);
 
diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v
index b27b9fe57..1bf427897 100644
--- a/tests/simple/peepopt.v
+++ b/tests/simple/peepopt.v
@@ -2,6 +2,10 @@ module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, in
 assign o = i[s*W+:W];
 endmodule
 
+module peepopt_shiftmul_1 (output y, input [2:0] w);
+assign y = 1'b1 >> (w * (3'b110));
+endmodule
+
 module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
 wire [3:0] t;
 assign t = i * 3;