From: lkcl <lkcl@web>
Date: Fri, 11 Dec 2020 16:25:29 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1405
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb298bbc21fa939617ebb7b98212e950cf50635b;p=libreriscv.git

---

diff --git a/simple_v_extension/appendix.mdwn b/simple_v_extension/appendix.mdwn
index d4a69b352..c0cfdc15c 100644
--- a/simple_v_extension/appendix.mdwn
+++ b/simple_v_extension/appendix.mdwn
@@ -1458,7 +1458,7 @@ circumstances it is perfectly fine to simply have the lanes
 "inactive" for predicated elements, even though it results in
 less than 100% ALU utilisation.
 
-## Twin-predication (based on source and destination register)
+## Twin-predication (based on source and destination register) <a name="tpred"></a>
 
 Twin-predication is not that much different, except that that
 the source is independently zero-predicated from the destination.