From: Florent Kermarrec Date: Tue, 15 Mar 2016 21:58:48 +0000 (+0100) Subject: soc/interconnect/stream: remove packetized parameter and use of sop X-Git-Tag: 24jan2021_ls180~1997 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb4737338358d7177f655cebef02c3a05956d2be;p=litex.git soc/interconnect/stream: remove packetized parameter and use of sop --- diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index 3ae860f5..87e079c2 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -14,13 +14,12 @@ def _make_m2s(layout): class EndpointDescription: - def __init__(self, payload_layout, param_layout=[], packetized=True): + def __init__(self, payload_layout, param_layout=[]): self.payload_layout = payload_layout self.param_layout = param_layout - self.packetized = packetized def get_full_layout(self): - reserved = {"stb", "ack", "payload", "param", "sop", "eop", "description"} + reserved = {"stb", "ack", "payload", "param", "eop", "description"} attributed = set() for f in self.payload_layout + self.param_layout: if f[0] in attributed: @@ -33,13 +32,9 @@ class EndpointDescription: ("payload", _make_m2s(self.payload_layout)), ("param", _make_m2s(self.param_layout)), ("stb", 1, DIR_M_TO_S), - ("ack", 1, DIR_S_TO_M) + ("ack", 1, DIR_S_TO_M), + ("eop", 1, DIR_M_TO_S) ] - if self.packetized: - full_layout += [ - ("sop", 1, DIR_M_TO_S), - ("eop", 1, DIR_M_TO_S) - ] return full_layout @@ -74,9 +69,8 @@ class _FIFOWrapper(Module): # # # description = self.sink.description - fifo_layout = [("payload", description.payload_layout)] - if description.packetized: - fifo_layout += [("sop", 1), ("eop", 1)] + fifo_layout = [("payload", description.payload_layout), + ("eop", 1)] self.submodules.fifo = fifo_class(layout_len(fifo_layout), depth) fifo_in = Record(fifo_layout) @@ -89,19 +83,14 @@ class _FIFOWrapper(Module): self.comb += [ self.sink.ack.eq(self.fifo.writable), self.fifo.we.eq(self.sink.stb), + fifo_in.eop.eq(self.sink.eop), fifo_in.payload.eq(self.sink.payload), self.source.stb.eq(self.fifo.readable), + self.source.eop.eq(fifo_out.eop), self.source.payload.eq(fifo_out.payload), self.fifo.re.eq(self.source.ack) ] - if description.packetized: - self.comb += [ - fifo_in.sop.eq(self.sink.sop), - fifo_in.eop.eq(self.sink.eop), - self.source.sop.eq(fifo_out.sop), - self.source.eop.eq(fifo_out.eop) - ] class SyncFIFO(_FIFOWrapper): @@ -199,14 +188,10 @@ class CombinatorialActor(BinaryActor): def build_binary_control(self, sink, source): self.comb += [ source.stb.eq(sink.stb), + source.eop.eq(sink.eop), sink.ack.eq(source.ack), self.busy.eq(0) ] - if sink.description.packetized: - self.comb += [ - source.sop.eq(sink.sop), - source.eop.eq(sink.eop) - ] class PipelinedActor(BinaryActor): @@ -229,24 +214,15 @@ class PipelinedActor(BinaryActor): source.stb.eq(valid), self.busy.eq(busy) ] - if sink.description.packetized: - sop = sink.stb & sink.sop - eop = sink.stb & sink.eop - for i in range(latency): - sop_n = Signal() - eop_n = Signal() - self.sync += \ - If(self.pipe_ce, - sop_n.eq(sop), - eop_n.eq(eop) - ) - sop = sop_n - eop = eop_n - - self.comb += [ - source.eop.eq(eop), - source.sop.eq(sop) - ] + eop = sink.stb & sink.eop + for i in range(latency): + eop_n = Signal() + self.sync += \ + If(self.pipe_ce, + eop_n.eq(eop) + ) + eop = eop_n + self.comb += source.eop.eq(eop) class Buffer(PipelinedActor): @@ -292,10 +268,8 @@ class Unpack(Module): # # # mux = Signal(max=n) - first = Signal() last = Signal() self.comb += [ - first.eq(mux == 0), last.eq(mux == (n-1)), source.stb.eq(sink.stb), sink.ack.eq(last & source.ack) @@ -320,11 +294,7 @@ class Unpack(Module): dst = getattr(self.source, f[0]) self.comb += dst.eq(src) - if description_from.packetized: - self.comb += [ - source.sop.eq(sink.sop & first), - source.eop.eq(sink.eop & last) - ] + self.comb += source.eop.eq(sink.eop & last) class Pack(Module): @@ -357,10 +327,7 @@ class Pack(Module): dst = getattr(self.source, f[0]) self.sync += If(load_part, dst.eq(src)) - if description_to.packetized: - demux_last = ((demux == (n - 1)) | sink.eop) - else: - demux_last = (demux == (n - 1)) + demux_last = ((demux == (n - 1)) | sink.eop) self.sync += [ If(source.ack, strobe_all.eq(0)), @@ -372,20 +339,14 @@ class Pack(Module): ).Else( demux.eq(demux + 1) ) + ), + If(source.stb & source.ack, + source.eop.eq(sink.eop), + ).Elif(sink.stb & sink.ack, + source.eop.eq(sink.eop | source.eop) ) ] - if description_to.packetized: - self.sync += [ - If(source.stb & source.ack, - source.sop.eq(sink.sop), - source.eop.eq(sink.eop), - ).Elif(sink.stb & sink.ack, - source.sop.eq(sink.sop | source.sop), - source.eop.eq(sink.eop | source.eop) - ) - ] - class Chunkerize(CombinatorialActor): def __init__(self, layout_from, layout_to, n, reverse=False): diff --git a/litex/soc/interconnect/stream_packet.py b/litex/soc/interconnect/stream_packet.py index a051ac21..1eb3b207 100644 --- a/litex/soc/interconnect/stream_packet.py +++ b/litex/soc/interconnect/stream_packet.py @@ -18,18 +18,25 @@ def reverse_bytes(signal): class Status(Module): def __init__(self, endpoint): - self.sop = sop = Signal() - self.eop = eop =Signal() + self.first = first = Signal(reset=1) + self.eop = eop = Signal() self.ongoing = Signal() ongoing = Signal() self.comb += \ If(endpoint.stb, - sop.eq(endpoint.sop), eop.eq(endpoint.eop & endpoint.ack) ) - self.sync += ongoing.eq((sop | ongoing) & ~eop) - self.comb += self.ongoing.eq((sop | ongoing) & ~eop) + self.sync += ongoing.eq((endpoint.stb | ongoing) & ~eop) + self.comb += self.ongoing.eq((endpoint.stb | ongoing) & ~eop) + + self.sync += [ + If(eop, + first.eq(1) + ).Elif(endpoint.stb & endpoint.ack, + first.eq(0) + ) + ] class Arbiter(Module): @@ -72,11 +79,11 @@ class Dispatcher(Module): sel = Signal.like(self.sel) sel_ongoing = Signal.like(self.sel) self.sync += \ - If(status.sop, + If(status.first, sel_ongoing.eq(self.sel) ) self.comb += \ - If(status.sop, + If(status.first, sel.eq(self.sel) ).Else( sel.eq(sel_ongoing) @@ -197,10 +204,9 @@ class Packetizer(Module): fsm.act("IDLE", sink.ack.eq(1), counter_reset.eq(1), - If(sink.stb & sink.sop, + If(sink.stb, sink.ack.eq(0), source.stb.eq(1), - source.sop.eq(1), source.eop.eq(0), source.data.eq(self.header[:dw]), If(source.stb & source.ack, @@ -212,7 +218,6 @@ class Packetizer(Module): if header_words != 1: fsm.act("SEND_HEADER", source.stb.eq(1), - source.sop.eq(0), source.eop.eq(0), source.data.eq(header_reg[dw:2*dw]), If(source.stb & source.ack, @@ -225,7 +230,6 @@ class Packetizer(Module): ) fsm.act("COPY", source.stb.eq(sink.stb), - source.sop.eq(0), source.eop.eq(sink.eop), source.data.eq(sink.data), source.error.eq(sink.error), @@ -302,10 +306,7 @@ class Depacketizer(Module): no_payload = Signal() self.sync += \ If(fsm.before_entering("COPY"), - source.sop.eq(1), no_payload.eq(sink.eop) - ).Elif(source.stb & source.ack, - source.sop.eq(0) ) if hasattr(sink, "error"): @@ -360,13 +361,6 @@ class Buffer(Module): self.submodules += fsm fsm.act("IDLE", If(cmd_fifo.source.stb, - NextState("SEEK_SOP") - ) - ) - fsm.act("SEEK_SOP", - If(~data_fifo.source.sop, - data_fifo.source.ack.eq(1) - ).Else( NextState("OUTPUT") ) ) diff --git a/litex/soc/interconnect/stream_sim.py b/litex/soc/interconnect/stream_sim.py index 16b64163..786418c4 100644 --- a/litex/soc/interconnect/stream_sim.py +++ b/litex/soc/interconnect/stream_sim.py @@ -120,21 +120,17 @@ class PacketStreamer(Module): self.packet = self.packets.pop(0) if not self.packet.ongoing and not self.packet.done: selfp.source.stb = 1 - if self.source.description.packetized: - selfp.source.sop = 1 selfp.source.data = self.packet.pop(0) self.packet.ongoing = True elif selfp.source.stb == 1 and selfp.source.ack == 1: - if self.source.description.packetized: - selfp.source.sop = 0 - if len(self.packet) == 1: - selfp.source.eop = 1 - if self.last_be is not None: - selfp.source.last_be = self.last_be - else: - selfp.source.eop = 0 - if self.last_be is not None: - selfp.source.last_be = 0 + if len(self.packet) == 1: + selfp.source.eop = 1 + if self.last_be is not None: + selfp.source.last_be = self.last_be + else: + selfp.source.eop = 0 + if self.last_be is not None: + selfp.source.last_be = 0 if len(self.packet) > 0: selfp.source.stb = 1 selfp.source.data = self.packet.pop(0) @@ -150,6 +146,7 @@ class PacketLogger(Module): # # # self.packet = Packet() + self.first = True def receive(self): self.packet.done = False @@ -159,16 +156,15 @@ class PacketLogger(Module): def do_simulation(self, selfp): selfp.sink.ack = 1 if selfp.sink.stb: - if self.sink.description.packetized: - if selfp.sink.sop: - self.packet = Packet() - self.packet.append(selfp.sink.data) - else: - self.packet.append(selfp.sink.data) - if selfp.sink.eop: - self.packet.done = True + if self.first: + self.packet = Packet() + self.packet.append(selfp.sink.data) + self.first = False else: self.packet.append(selfp.sink.data) + if selfp.sink.eop: + self.packet.done = True + self.first = True class AckRandomizer(Module): diff --git a/litex/soc/interconnect/wishbonebridge.py b/litex/soc/interconnect/wishbonebridge.py index 7448733d..a1a3ad1e 100644 --- a/litex/soc/interconnect/wishbonebridge.py +++ b/litex/soc/interconnect/wishbonebridge.py @@ -158,10 +158,7 @@ class WishboneStreamingBridge(Module): self.comb += timer.wait.eq(~fsm.ongoing("IDLE")) - if phy.sink.description.packetized: - self.comb += [ - phy.sink.sop.eq((byte_counter == 0) & (word_counter == 0)), - phy.sink.eop.eq((byte_counter == 3) & (word_counter == length - 1)) - ] - if hasattr(phy.sink, "length"): - self.comb += phy.sink.length.eq(4*length) + self.comb += phy.sink.eop.eq((byte_counter == 3) & (word_counter == length - 1)) + + if hasattr(phy.sink, "length"): + self.comb += phy.sink.length.eq(4*length)