From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 22 Aug 2014 10:26:25 +0000 (+0800)
Subject: platforms: add -w option to bitgen_opt
X-Git-Tag: 24jan2021_ls180~2099^2~314
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb5894b33c328da3313f75acaf5c459db0543a5a;p=litex.git

platforms: add -w option to bitgen_opt
---

diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py
index e259e4eb..08d61249 100644
--- a/mibuild/platforms/lx9_microboard.py
+++ b/mibuild/platforms/lx9_microboard.py
@@ -103,7 +103,7 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
-	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -g SPI_buswidth:4"
+	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
 	ise_commands = """
 promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
 """
diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py
index 97702555..720bed43 100644
--- a/mibuild/platforms/usrp_b100.py
+++ b/mibuild/platforms/usrp_b100.py
@@ -114,7 +114,7 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
-	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -g UnusedPin:PullUp"
+	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io,
 			lambda p: CRG_DS(p, "clk64", "reset_n", rst_invert=True))