From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 11 Jul 2021 15:02:15 +0000 (+0100)
Subject: add SVREMAP SPR
X-Git-Tag: xlen-bcd~299
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb5c27d2e554185352fcb281209a366c41241136;p=openpower-isa.git

add SVREMAP SPR
---

diff --git a/openpower/isatables/sprs.csv b/openpower/isatables/sprs.csv
index 6129170d..5acc87f6 100644
--- a/openpower/isatables/sprs.csv
+++ b/openpower/isatables/sprs.csv
@@ -70,14 +70,15 @@ Idx,SPR,priv_mtspr,priv_mfspr,len
 723,SVSHAPE1,yes,yes,32
 724,SVSHAPE2,yes,yes,32
 725,SVSHAPE3,yes,yes,32
-726,SVCTX0,yes,yes,64
-727,SVCTX1,yes,yes,64
-728,SVCTX2,yes,yes,64
-729,SVCTX3,yes,yes,64
-730,SVCTX4,yes,yes,64
-731,SVCTX5,yes,yes,64
-732,SVCTX6,yes,yes,64
-733,SVCTX7,yes,yes,64
+726,SVREMAP,yes,yes,32
+727,SVCTX0,yes,yes,64
+728,SVCTX1,yes,yes,64
+729,SVCTX2,yes,yes,64
+730,SVCTX3,yes,yes,64
+731,SVCTX4,yes,yes,64
+732,SVCTX5,yes,yes,64
+733,SVCTX6,yes,yes,64
+734,SVCTX7,yes,yes,64
 768,SIER,-,no,64
 769,MMCR2,no,no,64
 770,MMCRA,no,no,64
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index c598c4f6..e2cf01eb 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -74,6 +74,7 @@ REG_SORT_ORDER = {
     "TAR": 0,
     "MSR": 0,
     "SVSTATE": 0,
+    "SVREMAP": 0,
     "SVSHAPE0": 0,
     "SVSHAPE1": 0,
     "SVSHAPE2": 0,