From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 15 May 2021 19:09:54 +0000 (+0100)
Subject: FP mul test, correct pseudocode to use FRC
X-Git-Tag: 0.0.3~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb71f8342883992ee51f54275d4cee897a4f1745;p=openpower-isa.git

FP mul test, correct pseudocode to use FRC
---

diff --git a/openpower/isa/fparith.mdwn b/openpower/isa/fparith.mdwn
index 7bd434c8..2ce6a2cd 100644
--- a/openpower/isa/fparith.mdwn
+++ b/openpower/isa/fparith.mdwn
@@ -78,12 +78,12 @@ Special Registers Altered:
 
 A-Form
 
-* fmuls FRT,FRA,FRB (Rc=0)
-* fmuls. FRT,FRA,FRB (Rc=0)
+* fmuls FRT,FRA,FRC (Rc=0)
+* fmuls. FRT,FRA,FRC (Rc=0)
 
 Pseudo-code:
 
-    FRT <- FPMUL32(FRA, FRB)
+    FRT <- FPMUL32(FRA, FRC)
 
 Special Registers Altered:
 
@@ -96,12 +96,12 @@ Special Registers Altered:
 
 A-Form
 
-* fmul FRT,FRA,FRB (Rc=0)
-* fmul. FRT,FRA,FRB (Rc=0)
+* fmul FRT,FRA,FRC (Rc=0)
+* fmul. FRT,FRA,FRC (Rc=0)
 
 Pseudo-code:
 
-    FRT <- FPMUL64(FRA, FRB)
+    FRT <- FPMUL64(FRA, FRC)
 
 Special Registers Altered:
 
diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index a0635fc1..c2cbd4dd 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -178,6 +178,23 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
             self.assertEqual(sim.fpr(3), SelectableInt(0xC006666666666668, 64))
 
+    def test_fp_mul(self):
+        """>>> lst = ["fmul 3, 1, 2",
+                     ]
+        """
+        lst = ["fmul 3, 1, 2", # 7.0 * -9.8 = -68.6
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0x401C000000000000  # 7.0
+        fprs[2] = 0xC02399999999999A  # -9.8
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            self.assertEqual(sim.fpr(1), SelectableInt(0x401C000000000000, 64))
+            self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
+            self.assertEqual(sim.fpr(3), SelectableInt(0xC051266666666667, 64))
+
     def run_tst_program(self, prog, initial_regs=None,
                               initial_mem=None,
                               initial_fprs=None):