From: Gabe Black Date: Thu, 23 Jan 2020 05:21:48 +0000 (-0800) Subject: dev: Delete alpha devices. X-Git-Tag: v20.0.0.0~519 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb74a5d7ac623d634eb520cc7507cc91caab0cc8;p=gem5.git dev: Delete alpha devices. Change-Id: Idc41e83d94d39e8e45044a64b22b39cb395947c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24650 Tested-by: kokoro Maintainer: Jason Lowe-Power Reviewed-by: Bobby R. Bruce --- diff --git a/src/dev/alpha/AlphaBackdoor.py b/src/dev/alpha/AlphaBackdoor.py deleted file mode 100644 index 6355269fc..000000000 --- a/src/dev/alpha/AlphaBackdoor.py +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2005-2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Nathan Binkert - -from m5.defines import buildEnv -from m5.params import * -from m5.proxy import * - -from m5.objects.Device import BasicPioDevice - -class AlphaBackdoor(BasicPioDevice): - type = 'AlphaBackdoor' - cxx_header = "dev/alpha/backdoor.hh" - cpu = Param.BaseCPU(Parent.cpu[0], "Processor") - disk = Param.SimpleDisk("Simple Disk") - terminal = Param.Terminal(Parent.any, "The console terminal") - platform = Param.Platform(Parent.any, "Platform this device is part of.") - system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript deleted file mode 100644 index 9c8a5b4ce..000000000 --- a/src/dev/alpha/SConscript +++ /dev/null @@ -1,45 +0,0 @@ -# -*- mode:python -*- - -# Copyright (c) 2006 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Steve Reinhardt -# Gabe Black - -Import('*') - -if env['TARGET_ISA'] == 'alpha': - SimObject('AlphaBackdoor.py') - SimObject('Tsunami.py') - - Source('backdoor.cc') - Source('tsunami.cc') - Source('tsunami_cchip.cc') - Source('tsunami_io.cc') - Source('tsunami_pchip.cc') - - DebugFlag('AlphaBackdoor') - DebugFlag('Tsunami') diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py deleted file mode 100644 index e5b8885ad..000000000 --- a/src/dev/alpha/Tsunami.py +++ /dev/null @@ -1,133 +0,0 @@ -# Copyright (c) 2005-2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Nathan Binkert - -from m5.params import * -from m5.proxy import * -from m5.objects.BadDevice import BadDevice -from m5.objects.AlphaBackdoor import AlphaBackdoor -from m5.objects.Device import BasicPioDevice, IsaFake, BadAddr -from m5.objects.PciHost import GenericPciHost -from m5.objects.Platform import Platform -from m5.objects.Uart import Uart8250 - -class TsunamiCChip(BasicPioDevice): - type = 'TsunamiCChip' - cxx_header = "dev/alpha/tsunami_cchip.hh" - tsunami = Param.Tsunami(Parent.any, "Tsunami") - -class TsunamiIO(BasicPioDevice): - type = 'TsunamiIO' - cxx_header = "dev/alpha/tsunami_io.hh" - time = Param.Time('01/01/2009', - "System time to use ('Now' for actual time)") - year_is_bcd = Param.Bool(False, - "The RTC should interpret the year as a BCD value") - tsunami = Param.Tsunami(Parent.any, "Tsunami") - frequency = Param.Frequency('1024Hz', "frequency of interrupts") - -class TsunamiPChip(GenericPciHost): - type = 'TsunamiPChip' - cxx_header = "dev/alpha/tsunami_pchip.hh" - - conf_base = 0x801fe000000 - conf_size = "16MB" - - pci_pio_base = 0x801fc000000 - pci_mem_base = 0x80000000000 - - pio_addr = Param.Addr("Device Address") - pio_latency = Param.Latency('100ns', "Programmed IO latency") - - tsunami = Param.Tsunami(Parent.any, "Tsunami") - -class Tsunami(Platform): - type = 'Tsunami' - cxx_header = "dev/alpha/tsunami.hh" - system = Param.System(Parent.any, "system") - - cchip = TsunamiCChip(pio_addr=0x801a0000000) - pchip = TsunamiPChip(pio_addr=0x80180000000) - fake_sm_chip = IsaFake(pio_addr=0x801fc000370) - - fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) - fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) - fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) - fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) - - fake_ppc = IsaFake(pio_addr=0x801fc0003bb) - - fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) - - fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) - fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) - fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) - fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) - fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) - fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) - fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) - fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) - fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) - fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) - - fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) - fake_ata1 = IsaFake(pio_addr=0x801fc000170) - - fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') - io = TsunamiIO(pio_addr=0x801fc000000) - uart = Uart8250(pio_addr=0x801fc0003f8) - backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk) - - # Attach I/O devices to specified bus object. Can't do this - # earlier, since the bus object itself is typically defined at the - # System level. - def attachIO(self, bus): - self.cchip.pio = bus.master - self.pchip.pio = bus.master - self.fake_sm_chip.pio = bus.master - self.fake_uart1.pio = bus.master - self.fake_uart2.pio = bus.master - self.fake_uart3.pio = bus.master - self.fake_uart4.pio = bus.master - self.fake_ppc.pio = bus.master - self.fake_OROM.pio = bus.master - self.fake_pnp_addr.pio = bus.master - self.fake_pnp_write.pio = bus.master - self.fake_pnp_read0.pio = bus.master - self.fake_pnp_read1.pio = bus.master - self.fake_pnp_read2.pio = bus.master - self.fake_pnp_read3.pio = bus.master - self.fake_pnp_read4.pio = bus.master - self.fake_pnp_read5.pio = bus.master - self.fake_pnp_read6.pio = bus.master - self.fake_pnp_read7.pio = bus.master - self.fake_ata0.pio = bus.master - self.fake_ata1.pio = bus.master - self.fb.pio = bus.master - self.io.pio = bus.master - self.uart.pio = bus.master - self.backdoor.pio = bus.master diff --git a/src/dev/alpha/access.h b/src/dev/alpha/access.h deleted file mode 100644 index 72eb4950a..000000000 --- a/src/dev/alpha/access.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __ALPHA_ACCESS_H__ -#define __ALPHA_ACCESS_H__ - -/** @file - * System Console Memory Mapped Register Definition - */ - -#define ALPHA_ACCESS_VERSION (1305) - -#ifdef CONSOLE -typedef unsigned uint32_t; -typedef unsigned long uint64_t; -#endif - -// This structure hacked up from simos -struct AlphaAccess -{ - uint32_t last_offset; // 00: must be first field - uint32_t version; // 04: - uint32_t numCPUs; // 08: - uint32_t intrClockFrequency; // 0C: Hz - uint64_t cpuClock; // 10: MHz - uint64_t mem_size; // 18: - - // Loaded kernel - uint64_t kernStart; // 20: - uint64_t kernEnd; // 28: - uint64_t entryPoint; // 30: - - // console disk stuff - uint64_t diskUnit; // 38: - uint64_t diskCount; // 40: - uint64_t diskPAddr; // 48: - uint64_t diskBlock; // 50: - uint64_t diskOperation; // 58: - - // console simple output stuff - uint64_t outputChar; // 60: Placeholder for output - uint64_t inputChar; // 68: Placeholder for input - - // MP boot - uint64_t cpuStack[64]; // 70: -}; - -#endif // __ALPHA_ACCESS_H__ diff --git a/src/dev/alpha/backdoor.cc b/src/dev/alpha/backdoor.cc deleted file mode 100644 index 4374f1955..000000000 --- a/src/dev/alpha/backdoor.cc +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Ali Saidi - * Steve Reinhardt - * Erik Hallnor - */ - -/** @file - * Alpha Console Backdoor Definition - */ - -#include "dev/alpha/backdoor.hh" - -#include -#include - -#include "arch/alpha/system.hh" -#include "base/inifile.hh" -#include "base/str.hh" -#include "base/trace.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" -#include "debug/AlphaBackdoor.hh" -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/alpha/tsunami_io.hh" -#include "dev/platform.hh" -#include "dev/storage/simple_disk.hh" -#include "dev/serial/terminal.hh" -#include "mem/packet.hh" -#include "mem/packet_access.hh" -#include "mem/physical.hh" -#include "params/AlphaBackdoor.hh" -#include "sim/sim_object.hh" - -using namespace std; -using namespace AlphaISA; - -AlphaBackdoor::AlphaBackdoor(const Params *p) - : BasicPioDevice(p, sizeof(struct AlphaAccess)), - disk(p->disk), terminal(p->terminal), - system(p->system), cpu(p->cpu) -{ - alphaAccess = new Access(); - alphaAccess->last_offset = pioSize - 1; - - alphaAccess->version = ALPHA_ACCESS_VERSION; - alphaAccess->diskUnit = 1; - - alphaAccess->diskCount = 0; - alphaAccess->diskPAddr = 0; - alphaAccess->diskBlock = 0; - alphaAccess->diskOperation = 0; - alphaAccess->outputChar = 0; - alphaAccess->inputChar = 0; - std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack)); - -} - -void -AlphaBackdoor::startup() -{ - system->setAlphaAccess(pioAddr); - alphaAccess->numCPUs = system->numContexts(); - alphaAccess->kernStart = system->getKernelStart(); - alphaAccess->kernEnd = system->getKernelEnd(); - alphaAccess->entryPoint = system->getKernelEntry(); - alphaAccess->mem_size = system->memSize(); - alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz - Tsunami *tsunami = dynamic_cast(params()->platform); - if (!tsunami) - fatal("Platform is not Tsunami.\n"); - alphaAccess->intrClockFrequency = tsunami->io->frequency(); -} - -Tick -AlphaBackdoor::read(PacketPtr pkt) -{ - - /** XXX Do we want to push the addr munging to a bus brige or something? So - * the device has it's physical address and then the bridge adds on whatever - * machine dependent address swizzle is required? - */ - - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - - Addr daddr = pkt->getAddr() - pioAddr; - - pkt->makeAtomicResponse(); - - switch (pkt->getSize()) - { - case sizeof(uint32_t): - switch (daddr) - { - case offsetof(AlphaAccess, last_offset): - pkt->setLE(alphaAccess->last_offset); - break; - case offsetof(AlphaAccess, version): - pkt->setLE(alphaAccess->version); - break; - case offsetof(AlphaAccess, numCPUs): - pkt->setLE(alphaAccess->numCPUs); - break; - case offsetof(AlphaAccess, intrClockFrequency): - pkt->setLE(alphaAccess->intrClockFrequency); - break; - default: - /* Old console code read in everyting as a 32bit int - * we now break that for better error checking. - */ - pkt->setBadAddress(); - } - DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr, - pkt->getLE()); - break; - case sizeof(uint64_t): - switch (daddr) - { - case offsetof(AlphaAccess, inputChar): - pkt->setLE(terminal->console_in()); - break; - case offsetof(AlphaAccess, cpuClock): - pkt->setLE(alphaAccess->cpuClock); - break; - case offsetof(AlphaAccess, mem_size): - pkt->setLE(alphaAccess->mem_size); - break; - case offsetof(AlphaAccess, kernStart): - pkt->setLE(alphaAccess->kernStart); - break; - case offsetof(AlphaAccess, kernEnd): - pkt->setLE(alphaAccess->kernEnd); - break; - case offsetof(AlphaAccess, entryPoint): - pkt->setLE(alphaAccess->entryPoint); - break; - case offsetof(AlphaAccess, diskUnit): - pkt->setLE(alphaAccess->diskUnit); - break; - case offsetof(AlphaAccess, diskCount): - pkt->setLE(alphaAccess->diskCount); - break; - case offsetof(AlphaAccess, diskPAddr): - pkt->setLE(alphaAccess->diskPAddr); - break; - case offsetof(AlphaAccess, diskBlock): - pkt->setLE(alphaAccess->diskBlock); - break; - case offsetof(AlphaAccess, diskOperation): - pkt->setLE(alphaAccess->diskOperation); - break; - case offsetof(AlphaAccess, outputChar): - pkt->setLE(alphaAccess->outputChar); - break; - default: - int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / - sizeof(alphaAccess->cpuStack[0]); - - if (cpunum >= 0 && cpunum < 64) - pkt->setLE(alphaAccess->cpuStack[cpunum]); - else - panic("Unknown 64bit access, %#x\n", daddr); - } - DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr, - pkt->getLE()); - break; - default: - pkt->setBadAddress(); - } - return pioDelay; -} - -Tick -AlphaBackdoor::write(PacketPtr pkt) -{ - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - Addr daddr = pkt->getAddr() - pioAddr; - - uint64_t val = pkt->getLE(); - assert(pkt->getSize() == sizeof(uint64_t)); - - switch (daddr) { - case offsetof(AlphaAccess, diskUnit): - alphaAccess->diskUnit = val; - break; - - case offsetof(AlphaAccess, diskCount): - alphaAccess->diskCount = val; - break; - - case offsetof(AlphaAccess, diskPAddr): - alphaAccess->diskPAddr = val; - break; - - case offsetof(AlphaAccess, diskBlock): - alphaAccess->diskBlock = val; - break; - - case offsetof(AlphaAccess, diskOperation): - if (val == 0x13) - disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, - alphaAccess->diskCount); - else - panic("Invalid disk operation!"); - - break; - - case offsetof(AlphaAccess, outputChar): - terminal->writeData((char)(val & 0xff)); - break; - - default: - int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / - sizeof(alphaAccess->cpuStack[0]); - inform("Launching CPU %d @ %d", cpunum, curTick()); - assert(val > 0 && "Must not access primary cpu"); - if (cpunum >= 0 && cpunum < 64) - alphaAccess->cpuStack[cpunum] = val; - else - panic("Unknown 64bit access, %#x\n", daddr); - } - - pkt->makeAtomicResponse(); - - return pioDelay; -} - -void -AlphaBackdoor::Access::serialize(CheckpointOut &cp) const -{ - SERIALIZE_SCALAR(last_offset); - SERIALIZE_SCALAR(version); - SERIALIZE_SCALAR(numCPUs); - SERIALIZE_SCALAR(mem_size); - SERIALIZE_SCALAR(cpuClock); - SERIALIZE_SCALAR(intrClockFrequency); - SERIALIZE_SCALAR(kernStart); - SERIALIZE_SCALAR(kernEnd); - SERIALIZE_SCALAR(entryPoint); - SERIALIZE_SCALAR(diskUnit); - SERIALIZE_SCALAR(diskCount); - SERIALIZE_SCALAR(diskPAddr); - SERIALIZE_SCALAR(diskBlock); - SERIALIZE_SCALAR(diskOperation); - SERIALIZE_SCALAR(outputChar); - SERIALIZE_SCALAR(inputChar); - SERIALIZE_ARRAY(cpuStack,64); -} - -void -AlphaBackdoor::Access::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_SCALAR(last_offset); - UNSERIALIZE_SCALAR(version); - UNSERIALIZE_SCALAR(numCPUs); - UNSERIALIZE_SCALAR(mem_size); - UNSERIALIZE_SCALAR(cpuClock); - UNSERIALIZE_SCALAR(intrClockFrequency); - UNSERIALIZE_SCALAR(kernStart); - UNSERIALIZE_SCALAR(kernEnd); - UNSERIALIZE_SCALAR(entryPoint); - UNSERIALIZE_SCALAR(diskUnit); - UNSERIALIZE_SCALAR(diskCount); - UNSERIALIZE_SCALAR(diskPAddr); - UNSERIALIZE_SCALAR(diskBlock); - UNSERIALIZE_SCALAR(diskOperation); - UNSERIALIZE_SCALAR(outputChar); - UNSERIALIZE_SCALAR(inputChar); - UNSERIALIZE_ARRAY(cpuStack, 64); -} - -void -AlphaBackdoor::serialize(CheckpointOut &cp) const -{ - alphaAccess->serialize(cp); -} - -void -AlphaBackdoor::unserialize(CheckpointIn &cp) -{ - alphaAccess->unserialize(cp); -} - -AlphaBackdoor * -AlphaBackdoorParams::create() -{ - return new AlphaBackdoor(this); -} diff --git a/src/dev/alpha/backdoor.hh b/src/dev/alpha/backdoor.hh deleted file mode 100644 index 7dd369aaf..000000000 --- a/src/dev/alpha/backdoor.hh +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -/** @file - * System Console Backdoor Interface - */ - -#ifndef __DEV_ALPHA_BACKDOOR_HH__ -#define __DEV_ALPHA_BACKDOOR_HH__ - -#include "base/types.hh" -#include "dev/alpha/access.h" -#include "dev/io_device.hh" -#include "params/AlphaBackdoor.hh" -#include "sim/sim_object.hh" - -class BaseCPU; -class Terminal; -class AlphaSystem; -class SimpleDisk; - -/** - * Memory mapped interface to the system console. This device - * represents a shared data region between the OS Kernel and the - * System Console Backdoor. - * - * The system console is a small standalone program that is initially - * run when the system boots. It contains the necessary code to - * access the boot disk, to read/write from the console, and to pass - * boot parameters to the kernel. - * - * This version of the system console is very different from the one - * that would be found in a real system. Many of the functions use - * some sort of backdoor to get their job done. For example, reading - * from the boot device on a real system would require a minimal - * device driver to access the disk controller, but since we have a - * simulator here, we are able to bypass the disk controller and - * access the disk image directly. There are also some things like - * reading the kernel off the disk image into memory that are normally - * taken care of by the console that are now taken care of by the - * simulator. - * - * These shortcuts are acceptable since the system console is - * primarily used doing boot before the kernel has loaded its device - * drivers. - */ -class AlphaBackdoor : public BasicPioDevice -{ - protected: - struct Access : public AlphaAccess, public Serializable - { - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; - }; - - union { - Access *alphaAccess; - uint8_t *consoleData; - }; - - /** the disk must be accessed from the console */ - SimpleDisk *disk; - - /** the system console (the terminal) is accessable from the console */ - Terminal *terminal; - - /** a pointer to the system we are running in */ - AlphaSystem *system; - - /** a pointer to the CPU boot cpu */ - BaseCPU *cpu; - - public: - typedef AlphaBackdoorParams Params; - AlphaBackdoor(const Params *p); - - const Params * - params() const - { - return dynamic_cast(_params); - } - - void startup() override; - - /** - * memory mapped reads and writes - */ - Tick read(PacketPtr pkt) override; - Tick write(PacketPtr pkt) override; - - /** - * standard serialization routines for checkpointing - */ - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; -}; - -#endif // __DEV_ALPHA_BACKDOOR_HH__ diff --git a/src/dev/alpha/tsunami.cc b/src/dev/alpha/tsunami.cc deleted file mode 100644 index 3db7c496d..000000000 --- a/src/dev/alpha/tsunami.cc +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -/** @file - * Implementation of Tsunami platform. - */ - -#include "dev/alpha/tsunami.hh" - -#include -#include -#include - -#include "arch/alpha/system.hh" -#include "cpu/intr_control.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/alpha/tsunami_io.hh" -#include "dev/alpha/tsunami_pchip.hh" - -using namespace std; - -Tsunami::Tsunami(const Params *p) - : Platform(p), system(p->system) -{ - for (int i = 0; i < Tsunami::Max_CPUs; i++) - intr_sum_type[i] = 0; -} - -void -Tsunami::init() -{ - AlphaSystem *alphaSystem = dynamic_cast(system); - assert(alphaSystem); - alphaSystem->setIntrFreq(io->frequency()); -} - -void -Tsunami::postConsoleInt() -{ - io->postPIC(0x10); -} - -void -Tsunami::clearConsoleInt() -{ - io->clearPIC(0x10); -} - -void -Tsunami::postPciInt(int line) -{ - cchip->postDRIR(line); -} - -void -Tsunami::clearPciInt(int line) -{ - cchip->clearDRIR(line); -} - -void -Tsunami::serialize(CheckpointOut &cp) const -{ - SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs); -} - -void -Tsunami::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs); -} - -Tsunami * -TsunamiParams::create() -{ - return new Tsunami(this); -} diff --git a/src/dev/alpha/tsunami.hh b/src/dev/alpha/tsunami.hh deleted file mode 100644 index 00df27c5c..000000000 --- a/src/dev/alpha/tsunami.hh +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -/** - * @file - * Declaration of top level class for the Tsunami chipset. This class just - * retains pointers to all its children so the children can communicate. - */ - -#ifndef __DEV_TSUNAMI_HH__ -#define __DEV_TSUNAMI_HH__ - -#include "dev/platform.hh" -#include "params/Tsunami.hh" - -class IdeController; -class TsunamiCChip; -class TsunamiPChip; -class TsunamiIO; -class System; - -/** - * Top level class for Tsunami Chipset emulation. - * This structure just contains pointers to all the - * children so the children can commnicate to do the - * read work - */ - -class Tsunami : public Platform -{ - public: - /** Max number of CPUs in a Tsunami */ - static const int Max_CPUs = 64; - - /** Pointer to the system */ - System *system; - - /** Pointer to the TsunamiIO device which has the RTC */ - TsunamiIO *io; - - /** Pointer to the Tsunami CChip. - * The chip contains some configuration information and - * all the interrupt mask and status registers - */ - TsunamiCChip *cchip; - - /** Pointer to the Tsunami PChip. - * The pchip is the interface to the PCI bus, in our case - * it does not have to do much. - */ - TsunamiPChip *pchip; - - int intr_sum_type[Tsunami::Max_CPUs]; - int ipi_pending[Tsunami::Max_CPUs]; - - void init() override; - - public: - typedef TsunamiParams Params; - Tsunami(const Params *p); - - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; - - public: // Public Platform interfaces - void postConsoleInt() override; - void clearConsoleInt() override; - - void postPciInt(int line) override; - void clearPciInt(int line) override; -}; - -#endif // __DEV_TSUNAMI_HH__ diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc deleted file mode 100644 index b670898f4..000000000 --- a/src/dev/alpha/tsunami_cchip.cc +++ /dev/null @@ -1,532 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Ron Dreslinski - */ - -/** @file - * Emulation of the Tsunami CChip CSRs - */ - -#include "dev/alpha/tsunami_cchip.hh" - -#include -#include -#include - -#include "arch/alpha/ev5.hh" -#include "base/trace.hh" -#include "cpu/intr_control.hh" -#include "cpu/thread_context.hh" -#include "debug/IPI.hh" -#include "debug/Tsunami.hh" -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunamireg.h" -#include "mem/packet.hh" -#include "mem/packet_access.hh" -#include "mem/port.hh" -#include "params/TsunamiCChip.hh" -#include "sim/system.hh" - -TsunamiCChip::TsunamiCChip(const Params *p) - : BasicPioDevice(p, 0x10000000), tsunami(p->tsunami) -{ - drir = 0; - ipint = 0; - itint = 0; - - for (int x = 0; x < Tsunami::Max_CPUs; x++) - { - dim[x] = 0; - dir[x] = 0; - } - - //Put back pointer in tsunami - tsunami->cchip = this; -} - -Tick -TsunamiCChip::read(PacketPtr pkt) -{ - DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); - - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - - Addr regnum = (pkt->getAddr() - pioAddr) >> 6; - Addr daddr = (pkt->getAddr() - pioAddr); - - switch (pkt->getSize()) { - - case sizeof(uint64_t): - pkt->setLE(0); - - if (daddr & TSDEV_CC_BDIMS) - { - pkt->setLE(dim[(daddr >> 4) & 0x3F]); - break; - } - - if (daddr & TSDEV_CC_BDIRS) - { - pkt->setLE(dir[(daddr >> 4) & 0x3F]); - break; - } - - switch(regnum) { - case TSDEV_CC_CSR: - pkt->setLE(0x0); - break; - case TSDEV_CC_MTR: - panic("TSDEV_CC_MTR not implemeted\n"); - break; - case TSDEV_CC_MISC: - pkt->setLE(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) | - (pkt->req->contextId() & 0x3)); - // currently, FS cannot handle MT so contextId and - // cpuId are effectively the same, don't know if it will - // matter if FS becomes MT enabled. I suspect no because - // we are currently able to boot up to 64 procs anyway - // which would render the CPUID of this register useless - // anyway - break; - case TSDEV_CC_AAR0: - case TSDEV_CC_AAR1: - case TSDEV_CC_AAR2: - case TSDEV_CC_AAR3: - pkt->setLE(0); - break; - case TSDEV_CC_DIM0: - pkt->setLE(dim[0]); - break; - case TSDEV_CC_DIM1: - pkt->setLE(dim[1]); - break; - case TSDEV_CC_DIM2: - pkt->setLE(dim[2]); - break; - case TSDEV_CC_DIM3: - pkt->setLE(dim[3]); - break; - case TSDEV_CC_DIR0: - pkt->setLE(dir[0]); - break; - case TSDEV_CC_DIR1: - pkt->setLE(dir[1]); - break; - case TSDEV_CC_DIR2: - pkt->setLE(dir[2]); - break; - case TSDEV_CC_DIR3: - pkt->setLE(dir[3]); - break; - case TSDEV_CC_DRIR: - pkt->setLE(drir); - break; - case TSDEV_CC_PRBEN: - panic("TSDEV_CC_PRBEN not implemented\n"); - break; - case TSDEV_CC_IIC0: - case TSDEV_CC_IIC1: - case TSDEV_CC_IIC2: - case TSDEV_CC_IIC3: - panic("TSDEV_CC_IICx not implemented\n"); - break; - case TSDEV_CC_MPR0: - case TSDEV_CC_MPR1: - case TSDEV_CC_MPR2: - case TSDEV_CC_MPR3: - panic("TSDEV_CC_MPRx not implemented\n"); - break; - case TSDEV_CC_IPIR: - pkt->setLE(ipint); - break; - case TSDEV_CC_ITIR: - pkt->setLE(itint); - break; - default: - panic("default in cchip read reached, accessing 0x%x\n"); - } // uint64_t - - break; - case sizeof(uint32_t): - case sizeof(uint16_t): - case sizeof(uint8_t): - default: - panic("invalid access size(?) for tsunami register!\n"); - } - DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", - regnum, pkt->getSize(), pkt->getLE()); - - pkt->makeAtomicResponse(); - return pioDelay; -} - -Tick -TsunamiCChip::write(PacketPtr pkt) -{ - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - Addr daddr = pkt->getAddr() - pioAddr; - Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ; - - - assert(pkt->getSize() == sizeof(uint64_t)); - - DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", - pkt->getAddr(), pkt->getLE()); - - bool supportedWrite = false; - - - if (daddr & TSDEV_CC_BDIMS) - { - int number = (daddr >> 4) & 0x3F; - - uint64_t bitvector; - uint64_t olddim; - uint64_t olddir; - - olddim = dim[number]; - olddir = dir[number]; - dim[number] = pkt->getLE(); - dir[number] = dim[number] & drir; - for (int x = 0; x < Tsunami::Max_CPUs; x++) - { - bitvector = ULL(1) << x; - // Figure out which bits have changed - if ((dim[number] & bitvector) != (olddim & bitvector)) - { - // The bit is now set and it wasn't before (set) - if ((dim[number] & bitvector) && (dir[number] & bitvector)) - { - tsunami->intrctrl->post( - number, AlphaISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "dim write resulting in posting dir" - " interrupt to cpu %d\n", number); - } - else if ((olddir & bitvector) && - !(dir[number] & bitvector)) - { - // The bit was set and now its now clear and - // we were interrupting on that bit before - tsunami->intrctrl->clear( - number, AlphaISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "dim write resulting in clear" - " dir interrupt to cpu %d\n", number); - - } - - - } - } - } else { - switch(regnum) { - case TSDEV_CC_CSR: - panic("TSDEV_CC_CSR write\n"); - case TSDEV_CC_MTR: - panic("TSDEV_CC_MTR write not implemented\n"); - case TSDEV_CC_MISC: - uint64_t ipreq; - ipreq = (pkt->getLE() >> 12) & 0xF; - //If it is bit 12-15, this is an IPI post - if (ipreq) { - reqIPI(ipreq); - supportedWrite = true; - } - - //If it is bit 8-11, this is an IPI clear - uint64_t ipintr; - ipintr = (pkt->getLE() >> 8) & 0xF; - if (ipintr) { - clearIPI(ipintr); - supportedWrite = true; - } - - //If it is the 4-7th bit, clear the RTC interrupt - uint64_t itintr; - itintr = (pkt->getLE() >> 4) & 0xF; - if (itintr) { - clearITI(itintr); - supportedWrite = true; - } - - // ignore NXMs - if (pkt->getLE() & 0x10000000) - supportedWrite = true; - - if (!supportedWrite) - panic("TSDEV_CC_MISC write not implemented\n"); - - break; - case TSDEV_CC_AAR0: - case TSDEV_CC_AAR1: - case TSDEV_CC_AAR2: - case TSDEV_CC_AAR3: - panic("TSDEV_CC_AARx write not implemeted\n"); - case TSDEV_CC_DIM0: - case TSDEV_CC_DIM1: - case TSDEV_CC_DIM2: - case TSDEV_CC_DIM3: - int number; - if (regnum == TSDEV_CC_DIM0) - number = 0; - else if (regnum == TSDEV_CC_DIM1) - number = 1; - else if (regnum == TSDEV_CC_DIM2) - number = 2; - else - number = 3; - - uint64_t bitvector; - uint64_t olddim; - uint64_t olddir; - - olddim = dim[number]; - olddir = dir[number]; - dim[number] = pkt->getLE(); - dir[number] = dim[number] & drir; - for (int x = 0; x < 64; x++) { - bitvector = ULL(1) << x; - // Figure out which bits have changed - if ((dim[number] & bitvector) != (olddim & bitvector)) { - // The bit is now set and it wasn't before (set) - if ((dim[number] & bitvector) && - (dir[number] & bitvector)) { - tsunami->intrctrl->post( - number, AlphaISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, - "posting dir interrupt to cpu 0\n"); - } else if ((olddir & bitvector) && - !(dir[number] & bitvector)) { - // The bit was set and now its now clear and - // we were interrupting on that bit before - tsunami->intrctrl->clear( - number, AlphaISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "dim write resulting in clear" - " dir interrupt to cpu %d\n", x); - - } - - - } - } - break; - case TSDEV_CC_DIR0: - case TSDEV_CC_DIR1: - case TSDEV_CC_DIR2: - case TSDEV_CC_DIR3: - panic("TSDEV_CC_DIR write not implemented\n"); - case TSDEV_CC_DRIR: - panic("TSDEV_CC_DRIR write not implemented\n"); - case TSDEV_CC_PRBEN: - panic("TSDEV_CC_PRBEN write not implemented\n"); - case TSDEV_CC_IIC0: - case TSDEV_CC_IIC1: - case TSDEV_CC_IIC2: - case TSDEV_CC_IIC3: - panic("TSDEV_CC_IICx write not implemented\n"); - case TSDEV_CC_MPR0: - case TSDEV_CC_MPR1: - case TSDEV_CC_MPR2: - case TSDEV_CC_MPR3: - panic("TSDEV_CC_MPRx write not implemented\n"); - case TSDEV_CC_IPIR: - clearIPI(pkt->getLE()); - break; - case TSDEV_CC_ITIR: - clearITI(pkt->getLE()); - break; - case TSDEV_CC_IPIQ: - reqIPI(pkt->getLE()); - break; - default: - panic("default in cchip read reached, accessing 0x%x\n"); - } // swtich(regnum) - } // not BIG_TSUNAMI write - pkt->makeAtomicResponse(); - return pioDelay; -} - -void -TsunamiCChip::clearIPI(uint64_t ipintr) -{ - int numcpus = sys->threadContexts.size(); - assert(numcpus <= Tsunami::Max_CPUs); - - if (ipintr) { - for (int cpunum=0; cpunum < numcpus; cpunum++) { - // Check each cpu bit - uint64_t cpumask = ULL(1) << cpunum; - if (ipintr & cpumask) { - // Check if there is a pending ipi - if (ipint & cpumask) { - ipint &= ~cpumask; - tsunami->intrctrl->clear( - cpunum, AlphaISA::INTLEVEL_IRQ3, 0); - DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum); - } else { - warn("clear IPI for CPU=%d, but NO IPI\n", cpunum); - } - } - } - } - else - panic("Big IPI Clear, but not processors indicated\n"); -} - -void -TsunamiCChip::clearITI(uint64_t itintr) -{ - int numcpus = sys->threadContexts.size(); - assert(numcpus <= Tsunami::Max_CPUs); - - if (itintr) { - for (int i=0; i < numcpus; i++) { - uint64_t cpumask = ULL(1) << i; - if (itintr & cpumask & itint) { - tsunami->intrctrl->clear(i, AlphaISA::INTLEVEL_IRQ2, 0); - itint &= ~cpumask; - DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); - } - } - } else { - panic("Big ITI Clear, but not processors indicated\n"); - } -} - -void -TsunamiCChip::reqIPI(uint64_t ipreq) -{ - int numcpus = sys->threadContexts.size(); - assert(numcpus <= Tsunami::Max_CPUs); - - if (ipreq) { - for (int cpunum=0; cpunum < numcpus; cpunum++) { - // Check each cpu bit - uint64_t cpumask = ULL(1) << cpunum; - if (ipreq & cpumask) { - // Check if there is already an ipi (bits 8:11) - if (!(ipint & cpumask)) { - ipint |= cpumask; - tsunami->intrctrl->post( - cpunum, AlphaISA::INTLEVEL_IRQ3, 0); - DPRINTF(IPI, "send IPI cpu=%d\n", cpunum); - } else { - warn("post IPI for CPU=%d, but IPI already\n", cpunum); - } - } - } - } else { - panic("Big IPI Request, but not processors indicated\n"); - } -} - - -void -TsunamiCChip::postRTC() -{ - int size = sys->threadContexts.size(); - assert(size <= Tsunami::Max_CPUs); - - for (int i = 0; i < size; i++) { - uint64_t cpumask = ULL(1) << i; - if (!(cpumask & itint)) { - itint |= cpumask; - tsunami->intrctrl->post(i, AlphaISA::INTLEVEL_IRQ2, 0); - DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i); - } - } -} - -void -TsunamiCChip::postDRIR(uint32_t interrupt) -{ - uint64_t bitvector = ULL(1) << interrupt; - uint64_t size = sys->threadContexts.size(); - assert(size <= Tsunami::Max_CPUs); - drir |= bitvector; - - for (int i=0; i < size; i++) { - dir[i] = dim[i] & drir; - if (dim[i] & bitvector) { - tsunami->intrctrl->post(i, AlphaISA::INTLEVEL_IRQ1, interrupt); - DPRINTF(Tsunami, "posting dir interrupt to cpu %d," - "interrupt %d\n",i, interrupt); - } - } -} - -void -TsunamiCChip::clearDRIR(uint32_t interrupt) -{ - uint64_t bitvector = ULL(1) << interrupt; - uint64_t size = sys->threadContexts.size(); - assert(size <= Tsunami::Max_CPUs); - - if (drir & bitvector) - { - drir &= ~bitvector; - for (int i=0; i < size; i++) { - if (dir[i] & bitvector) { - tsunami->intrctrl->clear(i, AlphaISA::INTLEVEL_IRQ1, interrupt); - DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," - "interrupt %d\n",i, interrupt); - - } - dir[i] = dim[i] & drir; - } - } else { - DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); - } -} - - -void -TsunamiCChip::serialize(CheckpointOut &cp) const -{ - SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); - SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); - SERIALIZE_SCALAR(ipint); - SERIALIZE_SCALAR(itint); - SERIALIZE_SCALAR(drir); -} - -void -TsunamiCChip::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); - UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); - UNSERIALIZE_SCALAR(ipint); - UNSERIALIZE_SCALAR(itint); - UNSERIALIZE_SCALAR(drir); -} - -TsunamiCChip * -TsunamiCChipParams::create() -{ - return new TsunamiCChip(this); -} diff --git a/src/dev/alpha/tsunami_cchip.hh b/src/dev/alpha/tsunami_cchip.hh deleted file mode 100644 index b6ddd49bd..000000000 --- a/src/dev/alpha/tsunami_cchip.hh +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -/** @file - * Emulation of the Tsunami CChip CSRs - */ - -#ifndef __TSUNAMI_CCHIP_HH__ -#define __TSUNAMI_CCHIP_HH__ - -#include "dev/alpha/tsunami.hh" -#include "dev/io_device.hh" -#include "params/TsunamiCChip.hh" - -/** - * Tsunami CChip CSR Emulation. This device includes all the interrupt - * handling code for the chipset. - */ -class TsunamiCChip : public BasicPioDevice -{ - protected: - /** - * pointer to the tsunami object. - * This is our access to all the other tsunami - * devices. - */ - Tsunami *tsunami; - - /** - * The dims are device interrupt mask registers. - * One exists for each CPU, the DRIR X DIM = DIR - */ - uint64_t dim[Tsunami::Max_CPUs]; - - /** - * The dirs are device interrupt registers. - * One exists for each CPU, the DRIR X DIM = DIR - */ - uint64_t dir[Tsunami::Max_CPUs]; - - /** - * This register contains bits for each PCI interrupt - * that can occur. - */ - uint64_t drir; - - /** Indicator of which CPUs have an IPI interrupt */ - uint64_t ipint; - - /** Indicator of which CPUs have an RTC interrupt */ - uint64_t itint; - - public: - typedef TsunamiCChipParams Params; - /** - * Initialize the Tsunami CChip by setting all of the - * device register to 0. - * @param p params struct - */ - TsunamiCChip(const Params *p); - - const Params * - params() const - { - return dynamic_cast(_params); - } - - Tick read(PacketPtr pkt) override; - - Tick write(PacketPtr pkt) override; - - /** - * post an RTC interrupt to the CPU - */ - void postRTC(); - - /** - * post an interrupt to the CPU. - * @param interrupt the interrupt number to post (0-64) - */ - void postDRIR(uint32_t interrupt); - - /** - * clear an interrupt previously posted to the CPU. - * @param interrupt the interrupt number to post (0-64) - */ - void clearDRIR(uint32_t interrupt); - - /** - * post an ipi interrupt to the CPU. - * @param ipintr the cpu number to clear(bitvector) - */ - void clearIPI(uint64_t ipintr); - - /** - * clear a timer interrupt previously posted to the CPU. - * @param itintr the cpu number to clear(bitvector) - */ - void clearITI(uint64_t itintr); - - /** - * request an interrupt be posted to the CPU. - * @param ipreq the cpu number to interrupt(bitvector) - */ - void reqIPI(uint64_t ipreq); - - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; -}; - -#endif // __TSUNAMI_CCHIP_HH__ diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc deleted file mode 100644 index 9bfb1b637..000000000 --- a/src/dev/alpha/tsunami_io.cc +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Andrew Schultz - * Miguel Serrano - */ - -/** @file - * Tsunami I/O including PIC, PIT, RTC, DMA - */ - -#include "dev/alpha/tsunami_io.hh" - -#include - -#include -#include -#include - -#include "base/time.hh" -#include "base/trace.hh" -#include "debug/Tsunami.hh" -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/alpha/tsunamireg.h" -#include "dev/rtcreg.h" -#include "mem/packet.hh" -#include "mem/packet_access.hh" -#include "mem/port.hh" -#include "sim/system.hh" - -// clang complains about std::set being overloaded with Packet::set if -// we open up the entire namespace std -using std::string; -using std::ostream; - -TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p) - : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency), - tsunami(p->tsunami) -{ -} - -TsunamiIO::TsunamiIO(const Params *p) - : BasicPioDevice(p, 0x100), tsunami(p->tsunami), - pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p) -{ - // set the back pointer from tsunami to myself - tsunami->io = this; - - timerData = 0; - picr = 0; - picInterrupting = false; -} - -Tick -TsunamiIO::frequency() const -{ - return SimClock::Frequency / params()->frequency; -} - -Tick -TsunamiIO::read(PacketPtr pkt) -{ - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - - Addr daddr = pkt->getAddr() - pioAddr; - - DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(), - pkt->getSize(), daddr); - - if (pkt->getSize() == sizeof(uint8_t)) { - switch(daddr) { - // PIC1 mask read - case TSDEV_PIC1_MASK: - pkt->setLE(~mask1); - break; - case TSDEV_PIC2_MASK: - pkt->setLE(~mask2); - break; - case TSDEV_PIC1_ISR: - // !!! If this is modified 64bit case needs to be too - // Pal code has to do a 64 bit physical read because there is - // no load physical byte instruction - pkt->setLE(picr); - break; - case TSDEV_PIC2_ISR: - // PIC2 not implemnted... just return 0 - pkt->setLE(0x00); - break; - case TSDEV_TMR0_DATA: - pkt->setLE(pitimer.readCounter(0)); - break; - case TSDEV_TMR1_DATA: - pkt->setLE(pitimer.readCounter(1)); - break; - case TSDEV_TMR2_DATA: - pkt->setLE(pitimer.readCounter(2)); - break; - case TSDEV_RTC_DATA: - pkt->setLE(rtc.readData(rtcAddr)); - break; - case TSDEV_CTRL_PORTB: - if (pitimer.outputHigh(2)) - pkt->setLE(PORTB_SPKR_HIGH); - else - pkt->setLE(0x00); - break; - default: - panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize()); - } - } else if (pkt->getSize() == sizeof(uint64_t)) { - if (daddr == TSDEV_PIC1_ISR) - pkt->setLE(picr); - else - panic("I/O Read - invalid addr - va %#x size %d\n", - pkt->getAddr(), pkt->getSize()); - } else { - panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize()); - } - pkt->makeAtomicResponse(); - return pioDelay; -} - -Tick -TsunamiIO::write(PacketPtr pkt) -{ - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - Addr daddr = pkt->getAddr() - pioAddr; - - DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", - pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, - (uint32_t)pkt->getLE()); - - assert(pkt->getSize() == sizeof(uint8_t)); - - switch(daddr) { - case TSDEV_PIC1_MASK: - mask1 = ~(pkt->getLE()); - if ((picr & mask1) && !picInterrupting) { - picInterrupting = true; - tsunami->cchip->postDRIR(55); - DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); - } - if ((!(picr & mask1)) && picInterrupting) { - picInterrupting = false; - tsunami->cchip->clearDRIR(55); - DPRINTF(Tsunami, "clearing pic interrupt\n"); - } - break; - case TSDEV_PIC2_MASK: - mask2 = pkt->getLE(); - //PIC2 Not implemented to interrupt - break; - case TSDEV_PIC1_ACK: - // clear the interrupt on the PIC - picr &= ~(1 << (pkt->getLE() & 0xF)); - if (!(picr & mask1)) - tsunami->cchip->clearDRIR(55); - break; - case TSDEV_DMA1_MODE: - mode1 = pkt->getLE(); - break; - case TSDEV_DMA2_MODE: - mode2 = pkt->getLE(); - break; - case TSDEV_TMR0_DATA: - pitimer.writeCounter(0, pkt->getLE()); - break; - case TSDEV_TMR1_DATA: - pitimer.writeCounter(1, pkt->getLE()); - break; - case TSDEV_TMR2_DATA: - pitimer.writeCounter(2, pkt->getLE()); - break; - case TSDEV_TMR_CTRL: - pitimer.writeControl(pkt->getLE()); - break; - case TSDEV_RTC_ADDR: - rtcAddr = pkt->getLE(); - break; - case TSDEV_RTC_DATA: - rtc.writeData(rtcAddr, pkt->getLE()); - break; - case TSDEV_KBD: - case TSDEV_DMA1_CMND: - case TSDEV_DMA2_CMND: - case TSDEV_DMA1_MMASK: - case TSDEV_DMA2_MMASK: - case TSDEV_PIC2_ACK: - case TSDEV_DMA1_RESET: - case TSDEV_DMA2_RESET: - case TSDEV_DMA1_MASK: - case TSDEV_DMA2_MASK: - case TSDEV_CTRL_PORTB: - break; - default: - panic("I/O Write - va%#x size %d data %#x\n", - pkt->getAddr(), pkt->getSize(), pkt->getLE()); - } - - pkt->makeAtomicResponse(); - return pioDelay; -} - -void -TsunamiIO::postPIC(uint8_t bitvector) -{ - //PIC2 Is not implemented, because nothing of interest there - picr |= bitvector; - if (picr & mask1) { - tsunami->cchip->postDRIR(55); - DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); - } -} - -void -TsunamiIO::clearPIC(uint8_t bitvector) -{ - //PIC2 Is not implemented, because nothing of interest there - picr &= ~bitvector; - if (!(picr & mask1)) { - tsunami->cchip->clearDRIR(55); - DPRINTF(Tsunami, "clearing pic interrupt to cchip\n"); - } -} - -void -TsunamiIO::serialize(CheckpointOut &cp) const -{ - SERIALIZE_SCALAR(rtcAddr); - SERIALIZE_SCALAR(timerData); - SERIALIZE_SCALAR(mask1); - SERIALIZE_SCALAR(mask2); - SERIALIZE_SCALAR(mode1); - SERIALIZE_SCALAR(mode2); - SERIALIZE_SCALAR(picr); - SERIALIZE_SCALAR(picInterrupting); - - // Serialize the timers - pitimer.serialize("pitimer", cp); - rtc.serialize("rtc", cp); -} - -void -TsunamiIO::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_SCALAR(rtcAddr); - UNSERIALIZE_SCALAR(timerData); - UNSERIALIZE_SCALAR(mask1); - UNSERIALIZE_SCALAR(mask2); - UNSERIALIZE_SCALAR(mode1); - UNSERIALIZE_SCALAR(mode2); - UNSERIALIZE_SCALAR(picr); - UNSERIALIZE_SCALAR(picInterrupting); - - // Unserialize the timers - pitimer.unserialize("pitimer", cp); - rtc.unserialize("rtc", cp); -} - -void -TsunamiIO::startup() -{ - rtc.startup(); - pitimer.startup(); -} - -TsunamiIO * -TsunamiIOParams::create() -{ - return new TsunamiIO(this); -} diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh deleted file mode 100644 index d7fac22e4..000000000 --- a/src/dev/alpha/tsunami_io.hh +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Andrew Schultz - * Miguel Serrano - */ - -/** @file - * Tsunami I/O Space mapping including RTC/timer interrupts - */ - -#ifndef __DEV_TSUNAMI_IO_HH__ -#define __DEV_TSUNAMI_IO_HH__ - -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/intel_8254_timer.hh" -#include "dev/io_device.hh" -#include "dev/mc146818.hh" -#include "params/TsunamiIO.hh" -#include "sim/eventq.hh" - -/** - * Tsunami I/O device is a catch all for all the south bridge stuff we care - * to implement. - */ -class TsunamiIO : public BasicPioDevice -{ - - protected: - - class RTC : public MC146818 - { - public: - Tsunami *tsunami; - RTC(const std::string &n, const TsunamiIOParams *p); - - protected: - void handleEvent() - { - //Actually interrupt the processor here - tsunami->cchip->postRTC(); - } - }; - - /** Mask of the PIC1 */ - uint8_t mask1; - - /** Mask of the PIC2 */ - uint8_t mask2; - - /** Mode of PIC1. Not used for anything */ - uint8_t mode1; - - /** Mode of PIC2. Not used for anything */ - uint8_t mode2; - - /** Raw PIC interrupt register before masking */ - uint8_t picr; //Raw PIC interrput register - - /** Is the pic interrupting right now or not. */ - bool picInterrupting; - - /** A pointer to the Tsunami device which be belong to */ - Tsunami *tsunami; - - /** Intel 8253 Periodic Interval Timer */ - Intel8254Timer pitimer; - - RTC rtc; - - uint8_t rtcAddr; - - /** The interval is set via two writes to the PIT. - * This variable contains a flag as to how many writes have happened, and - * the time so far. - */ - uint16_t timerData; - - public: - /** - * Return the freqency of the RTC - * @return interrupt rate of the RTC - */ - Tick frequency() const; - - public: - typedef TsunamiIOParams Params; - /** - * Initialize all the data for devices supported by Tsunami I/O. - * @param p pointer to Params struct - */ - TsunamiIO(const Params *p); - - const Params * - params() const - { - return dynamic_cast(_params); - } - - Tick read(PacketPtr pkt) override; - Tick write(PacketPtr pkt) override; - - /** - * Post an PIC interrupt to the CPU via the CChip - * @param bitvector interrupt to post. - */ - void postPIC(uint8_t bitvector); - - /** - * Clear a posted interrupt - * @param bitvector interrupt to clear - */ - void clearPIC(uint8_t bitvector); - - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; - - /** - * Start running. - */ - void startup() override; - -}; - -#endif // __DEV_TSUNAMI_IO_HH__ diff --git a/src/dev/alpha/tsunami_pchip.cc b/src/dev/alpha/tsunami_pchip.cc deleted file mode 100644 index 82f6f2167..000000000 --- a/src/dev/alpha/tsunami_pchip.cc +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Andrew Schultz - */ - -/** @file - * Tsunami PChip (pci) - */ -#include "dev/alpha/tsunami_pchip.hh" - -#include -#include -#include - -#include "base/trace.hh" -#include "debug/Tsunami.hh" -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/alpha/tsunamireg.h" -#include "dev/pci/device.hh" -#include "mem/packet.hh" -#include "mem/packet_access.hh" -#include "sim/system.hh" - -using namespace std; - -TsunamiPChip::TsunamiPChip(const Params *p) - : GenericPciHost(p), - pioRange(RangeSize(p->pio_addr, 0x1000)), - pioDelay(p->pio_latency) -{ - for (int i = 0; i < 4; i++) { - wsba[i] = 0; - wsm[i] = 0; - tba[i] = 0; - } - - // initialize pchip control register - pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36); - - //Set back pointer in tsunami - p->tsunami->pchip = this; -} - -Tick -TsunamiPChip::read(PacketPtr pkt) -{ - // We only need to handle our own configuration registers, pass - // unknown addresses to the generic code. - if (!pioRange.contains(pkt->getAddr())) - return GenericPciHost::read(pkt); - - Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;; - assert(pkt->getSize() == sizeof(uint64_t)); - - - DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); - - switch(daddr) { - case TSDEV_PC_WSBA0: - pkt->setLE(wsba[0]); - break; - case TSDEV_PC_WSBA1: - pkt->setLE(wsba[1]); - break; - case TSDEV_PC_WSBA2: - pkt->setLE(wsba[2]); - break; - case TSDEV_PC_WSBA3: - pkt->setLE(wsba[3]); - break; - case TSDEV_PC_WSM0: - pkt->setLE(wsm[0]); - break; - case TSDEV_PC_WSM1: - pkt->setLE(wsm[1]); - break; - case TSDEV_PC_WSM2: - pkt->setLE(wsm[2]); - break; - case TSDEV_PC_WSM3: - pkt->setLE(wsm[3]); - break; - case TSDEV_PC_TBA0: - pkt->setLE(tba[0]); - break; - case TSDEV_PC_TBA1: - pkt->setLE(tba[1]); - break; - case TSDEV_PC_TBA2: - pkt->setLE(tba[2]); - break; - case TSDEV_PC_TBA3: - pkt->setLE(tba[3]); - break; - case TSDEV_PC_PCTL: - pkt->setLE(pctl); - break; - case TSDEV_PC_PLAT: - panic("PC_PLAT not implemented\n"); - case TSDEV_PC_RES: - panic("PC_RES not implemented\n"); - case TSDEV_PC_PERROR: - pkt->setLE((uint64_t)0x00); - break; - case TSDEV_PC_PERRMASK: - pkt->setLE((uint64_t)0x00); - break; - case TSDEV_PC_PERRSET: - panic("PC_PERRSET not implemented\n"); - case TSDEV_PC_TLBIV: - panic("PC_TLBIV not implemented\n"); - case TSDEV_PC_TLBIA: - pkt->setLE((uint64_t)0x00); // shouldn't be readable, but linux - break; - case TSDEV_PC_PMONCTL: - panic("PC_PMONCTL not implemented\n"); - case TSDEV_PC_PMONCNT: - panic("PC_PMONCTN not implemented\n"); - default: - panic("Default in PChip Read reached reading 0x%x\n", daddr); - } - - pkt->makeAtomicResponse(); - return pioDelay; - -} - -Tick -TsunamiPChip::write(PacketPtr pkt) -{ - // We only need to handle our own configuration registers, pass - // unknown addresses to the generic code. - if (!pioRange.contains(pkt->getAddr())) - return GenericPciHost::write(pkt); - - Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6; - - assert(pkt->getSize() == sizeof(uint64_t)); - - DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); - - switch(daddr) { - case TSDEV_PC_WSBA0: - wsba[0] = pkt->getLE(); - break; - case TSDEV_PC_WSBA1: - wsba[1] = pkt->getLE(); - break; - case TSDEV_PC_WSBA2: - wsba[2] = pkt->getLE(); - break; - case TSDEV_PC_WSBA3: - wsba[3] = pkt->getLE(); - break; - case TSDEV_PC_WSM0: - wsm[0] = pkt->getLE(); - break; - case TSDEV_PC_WSM1: - wsm[1] = pkt->getLE(); - break; - case TSDEV_PC_WSM2: - wsm[2] = pkt->getLE(); - break; - case TSDEV_PC_WSM3: - wsm[3] = pkt->getLE(); - break; - case TSDEV_PC_TBA0: - tba[0] = pkt->getLE(); - break; - case TSDEV_PC_TBA1: - tba[1] = pkt->getLE(); - break; - case TSDEV_PC_TBA2: - tba[2] = pkt->getLE(); - break; - case TSDEV_PC_TBA3: - tba[3] = pkt->getLE(); - break; - case TSDEV_PC_PCTL: - pctl = pkt->getLE(); - break; - case TSDEV_PC_PLAT: - panic("PC_PLAT not implemented\n"); - case TSDEV_PC_RES: - panic("PC_RES not implemented\n"); - case TSDEV_PC_PERROR: - break; - case TSDEV_PC_PERRMASK: - panic("PC_PERRMASK not implemented\n"); - case TSDEV_PC_PERRSET: - panic("PC_PERRSET not implemented\n"); - case TSDEV_PC_TLBIV: - panic("PC_TLBIV not implemented\n"); - case TSDEV_PC_TLBIA: - break; // value ignored, supposted to invalidate SG TLB - case TSDEV_PC_PMONCTL: - panic("PC_PMONCTL not implemented\n"); - case TSDEV_PC_PMONCNT: - panic("PC_PMONCTN not implemented\n"); - default: - panic("Default in PChip write reached reading 0x%x\n", daddr); - - } // uint64_t - - pkt->makeAtomicResponse(); - return pioDelay; -} - - -AddrRangeList -TsunamiPChip::getAddrRanges() const -{ - return AddrRangeList({ - RangeSize(confBase, confSize), - pioRange - }); -} - - -#define DMA_ADDR_MASK ULL(0x3ffffffff) - -Addr -TsunamiPChip::dmaAddr(const PciBusAddr &dev, Addr busAddr) const -{ - // compare the address to the window base registers - uint64_t tbaMask = 0; - uint64_t baMask = 0; - - uint64_t windowMask = 0; - uint64_t windowBase = 0; - - uint64_t pteEntry = 0; - - Addr pteAddr; - Addr dmaAddr; - - for (int i = 0; i < 4; i++) { - - windowBase = wsba[i]; - windowMask = ~wsm[i] & (ULL(0xfff) << 20); - - if ((busAddr & windowMask) == (windowBase & windowMask)) { - - if (wsba[i] & 0x1) { // see if enabled - if (wsba[i] & 0x2) { // see if SG bit is set - /** @todo - This currently is faked by just doing a direct - read from memory, however, to be realistic, this - needs to actually do a bus transaction. The process - is explained in the tsunami documentation on page - 10-12 and basically munges the address to look up a - PTE from a table in memory and then uses that mapping - to create an address for the SG page - */ - - tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | - ULL(0x3ff)); - baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13); - pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10); - - sys->physProxy.readBlob(pteAddr, &pteEntry, - sizeof(uint64_t)); - - dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | - (busAddr & ULL(0x1fff)); - - } else { - baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff); - tbaMask = ~baMask; - dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask); - } - - return (dmaAddr & DMA_ADDR_MASK); - } - } - } - - // if no match was found, then return the original address - return busAddr; -} - -void -TsunamiPChip::serialize(CheckpointOut &cp) const -{ - SERIALIZE_SCALAR(pctl); - SERIALIZE_ARRAY(wsba, 4); - SERIALIZE_ARRAY(wsm, 4); - SERIALIZE_ARRAY(tba, 4); -} - -void -TsunamiPChip::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_SCALAR(pctl); - UNSERIALIZE_ARRAY(wsba, 4); - UNSERIALIZE_ARRAY(wsm, 4); - UNSERIALIZE_ARRAY(tba, 4); -} - - -TsunamiPChip * -TsunamiPChipParams::create() -{ - return new TsunamiPChip(this); -} diff --git a/src/dev/alpha/tsunami_pchip.hh b/src/dev/alpha/tsunami_pchip.hh deleted file mode 100644 index 212727d61..000000000 --- a/src/dev/alpha/tsunami_pchip.hh +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -/** @file - * Tsunami PCI interface CSRs - */ - -#ifndef __TSUNAMI_PCHIP_HH__ -#define __TSUNAMI_PCHIP_HH__ - -#include "dev/alpha/tsunami.hh" -#include "dev/pci/host.hh" -#include "params/TsunamiPChip.hh" - -/** - * A very simple implementation of the Tsunami PCI interface chips. - */ -class TsunamiPChip : public GenericPciHost -{ - protected: - - /** Pchip control register */ - uint64_t pctl; - - /** Window Base addresses */ - uint64_t wsba[4]; - - /** Window masks */ - uint64_t wsm[4]; - - /** Translated Base Addresses */ - uint64_t tba[4]; - - public: - typedef TsunamiPChipParams Params; - /** - * Register the PChip with the mmu and init all wsba, wsm, and tba to 0 - * @param p pointer to the parameters struct - */ - TsunamiPChip(const Params *p); - - const Params * - params() const - { - return dynamic_cast(_params); - } - - - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; - - public: - Tick read(PacketPtr pkt) override; - Tick write(PacketPtr pkt) override; - - AddrRangeList getAddrRanges() const override; - - /** - * Translate a PCI bus address to a memory address for DMA. - * @todo Andrew says this needs to be fixed. What's wrong with it? - * @param pci_addr PCI address to translate. - * @return memory system address - */ - Addr dmaAddr(const PciBusAddr &addr, Addr pci_addr) const override; - - protected: - const AddrRange pioRange; - const Tick pioDelay; -}; - -#endif // __TSUNAMI_PCHIP_HH__ diff --git a/src/dev/alpha/tsunamireg.h b/src/dev/alpha/tsunamireg.h deleted file mode 100644 index a2742e36d..000000000 --- a/src/dev/alpha/tsunamireg.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -/** @file - * List of Tsunami CSRs - */ - -#ifndef __TSUNAMIREG_H__ -#define __TSUNAMIREG_H__ - -#define ALPHA_K0SEG_BASE ULL(0xfffffc0000000000) - -// CChip Registers -#define TSDEV_CC_CSR 0x00 -#define TSDEV_CC_MTR 0x01 -#define TSDEV_CC_MISC 0x02 - -#define TSDEV_CC_AAR0 0x04 -#define TSDEV_CC_AAR1 0x05 -#define TSDEV_CC_AAR2 0x06 -#define TSDEV_CC_AAR3 0x07 -#define TSDEV_CC_DIM0 0x08 -#define TSDEV_CC_DIM1 0x09 -#define TSDEV_CC_DIR0 0x0A -#define TSDEV_CC_DIR1 0x0B -#define TSDEV_CC_DRIR 0x0C -#define TSDEV_CC_PRBEN 0x0D -#define TSDEV_CC_IIC0 0x0E -#define TSDEV_CC_IIC1 0x0F -#define TSDEV_CC_MPR0 0x10 -#define TSDEV_CC_MPR1 0x11 -#define TSDEV_CC_MPR2 0x12 -#define TSDEV_CC_MPR3 0x13 - -#define TSDEV_CC_DIM2 0x18 -#define TSDEV_CC_DIM3 0x19 -#define TSDEV_CC_DIR2 0x1A -#define TSDEV_CC_DIR3 0x1B -#define TSDEV_CC_IIC2 0x1C -#define TSDEV_CC_IIC3 0x1D - -// BigTsunami Registers -#define TSDEV_CC_BDIMS 0x1000000 -#define TSDEV_CC_BDIRS 0x2000000 -#define TSDEV_CC_IPIQ 0x20 //0xf01a000800 -#define TSDEV_CC_IPIR 0x21 //0xf01a000840 -#define TSDEV_CC_ITIR 0x22 //0xf01a000880 - - -// PChip Registers -#define TSDEV_PC_WSBA0 0x00 -#define TSDEV_PC_WSBA1 0x01 -#define TSDEV_PC_WSBA2 0x02 -#define TSDEV_PC_WSBA3 0x03 -#define TSDEV_PC_WSM0 0x04 -#define TSDEV_PC_WSM1 0x05 -#define TSDEV_PC_WSM2 0x06 -#define TSDEV_PC_WSM3 0x07 -#define TSDEV_PC_TBA0 0x08 -#define TSDEV_PC_TBA1 0x09 -#define TSDEV_PC_TBA2 0x0A -#define TSDEV_PC_TBA3 0x0B -#define TSDEV_PC_PCTL 0x0C -#define TSDEV_PC_PLAT 0x0D -#define TSDEV_PC_RES 0x0E -#define TSDEV_PC_PERROR 0x0F -#define TSDEV_PC_PERRMASK 0x10 -#define TSDEV_PC_PERRSET 0x11 -#define TSDEV_PC_TLBIV 0x12 -#define TSDEV_PC_TLBIA 0x13 -#define TSDEV_PC_PMONCTL 0x14 -#define TSDEV_PC_PMONCNT 0x15 - -#define TSDEV_PC_SPST 0x20 - - -// DChip Registers -#define TSDEV_DC_DSC 0x20 -#define TSDEV_DC_STR 0x21 -#define TSDEV_DC_DREV 0x22 -#define TSDEV_DC_DSC2 0x23 - -// I/O Ports -#define TSDEV_PIC1_MASK 0x21 -#define TSDEV_PIC2_MASK 0xA1 -#define TSDEV_PIC1_ISR 0x20 -#define TSDEV_PIC2_ISR 0xA0 -#define TSDEV_PIC1_ACK 0x20 -#define TSDEV_PIC2_ACK 0xA0 -#define TSDEV_DMA1_RESET 0x0D -#define TSDEV_DMA2_RESET 0xDA -#define TSDEV_DMA1_MODE 0x0B -#define TSDEV_DMA2_MODE 0xD6 -#define TSDEV_DMA1_MASK 0x0A -#define TSDEV_DMA2_MASK 0xD4 -#define TSDEV_CTRL_PORTB 0x61 -#define TSDEV_TMR0_DATA 0x40 -#define TSDEV_TMR1_DATA 0x41 -#define TSDEV_TMR2_DATA 0x42 -#define TSDEV_TMR_CTRL 0x43 -#define TSDEV_KBD 0x64 -#define TSDEV_DMA1_CMND 0x08 -#define TSDEV_DMA1_STAT TSDEV_DMA1_CMND -#define TSDEV_DMA2_CMND 0xD0 -#define TSDEV_DMA2_STAT TSDEV_DMA2_CMND -#define TSDEV_DMA1_MMASK 0x0F -#define TSDEV_DMA2_MMASK 0xDE - -/* Added for keyboard accesses */ -#define TSDEV_KBD 0x64 - -#define TSDEV_RTC_ADDR 0x70 -#define TSDEV_RTC_DATA 0x71 - -#define PCHIP_PCI0_MEMORY ULL(0x00000000000) -#define PCHIP_PCI0_IO ULL(0x001FC000000) -#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) -#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY -#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO - - -// System Control PortB Status Bits -#define PORTB_SPKR_HIGH 0x20 - -#endif // __TSUNAMIREG_H__ diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh index 1223e3b22..efa3e7922 100644 --- a/src/dev/isa_fake.hh +++ b/src/dev/isa_fake.hh @@ -38,7 +38,6 @@ #include #include "dev/io_device.hh" -// #include "dev/alpha/tsunami.hh" #include "mem/packet.hh" #include "params/IsaFake.hh"