From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Aug 2022 11:24:02 +0000 (+0100)
Subject: remove use of sv ld shifted, replace with els, deprecate the unit test
X-Git-Tag: sv_maxu_works-initial~169
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb9bb0c8de4cc4483aa77d7b3981bfd478e43932;p=openpower-isa.git

remove use of sv ld shifted, replace with els, deprecate the unit test
---

diff --git a/openpower/isa/svfpload.mdwn b/openpower/isa/svfpload.mdwn
deleted file mode 100644
index d8856c50..00000000
--- a/openpower/isa/svfpload.mdwn
+++ /dev/null
@@ -1,72 +0,0 @@
-<!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 4.6.1 Floating-point storage access instructions. P 140 - 143 -->
-
-# Load Floating-Point Single
-
-SVD-Form
-
-* lfssh FRT,SVD(RA),RC
-
-Pseudo-code:
-
-    b <- (RA|0)
-    n <- (RC)[58:63]
-    EA <- b + SHL64(srcstep * EXTS(SVD), n)
-    FRT <- DOUBLE(MEM(EA, 4))
-
-Special Registers Altered:
-
-    None
-
-# Load Floating-Point Single with Update
-
-SVD-Form
-
-* lfsush FRT,SVD(RA),RC
-
-Pseudo-code:
-
-    n <- (RC)[58:63]
-    EA <- (RA) + SHL64(srcstep * EXTS(SVD), n)
-    FRT <- DOUBLE(MEM(EA, 4))
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Floating-Point Double
-
-SVD-Form
-
-* lfdsh FRT,SVD(RA),RC
-
-Pseudo-code:
-
-    b <- (RA|0)
-    n <- (RC)[58:63]
-    EA <- b + SHL64(srcstep * EXTS(SVD), n)
-    FRT <- MEM(EA, 8)
-
-Special Registers Altered:
-
-    None
-
-# Load Floating-Point Double with Update
-
-SVD-Form
-
-* lfdush FRT,SVD(RA),RC
-
-Pseudo-code:
-
-    n <- (RC)[58:63]
-    EA <- (RA) + SHL64(srcstep * EXTS(SVD), n)
-    FRT <- MEM(EA, 8)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
diff --git a/src/openpower/decoder/isa/test_caller_svp64_ldst.py b/src/openpower/decoder/isa/test_caller_svp64_ldst.py
index 4fd2ecde..4e1901df 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_ldst.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_ldst.py
@@ -118,6 +118,7 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(12), SelectableInt(0x1234, 64))
             self.assertEqual(sim.gpr(13), SelectableInt(0x1235, 64))
 
+    @unittest.skip("deprecated, needs Scalar LDST-shifted")
     def test_sv_load_store_shifted(self):
         """>>> lst = ["addi 1, 0, 0x0010",
                         "addi 2, 0, 0x0004",
@@ -177,6 +178,7 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(14), SelectableInt(0x303, 64))
             self.assertEqual(sim.gpr(15), SelectableInt(0x404, 64))
 
+    @unittest.skip("deprecated, needs Scalar LDST-shifted")
     def test_sv_load_store_shifted_fp(self):
         """>>> lst = ["addi 1, 0, 0x0010",
                         "addi 2, 0, 0x0004",
@@ -334,7 +336,6 @@ class DecoderTestCase(FHDLTestCase):
                         "svshape 3, 3, 4, 0, 0",
                         "svremap 1, 1, 2, 0, 0, 0, 0",
                         "sv.lwz *20, 0(1)",
-                        #"sv.lwzsh *12, 4(1), 2", # bit-reversed
                         ])
         lst = list(lst)
 
@@ -391,7 +392,7 @@ class DecoderTestCase(FHDLTestCase):
                         "sv.stw *5, 0(1)",
                         "svshape 8, 1, 1, 6, 0",
                         "svremap 31, 1, 2, 3, 0, 0, 0",
-                        "sv.lwzsh *12, 4(1), 2"]
+                        "sv.lwz/els *12, 4(1)"]
 
         shifted LD is computed as:
         for i in range(VL):
@@ -420,7 +421,7 @@ class DecoderTestCase(FHDLTestCase):
                         "svshape 8, 1, 1, 6, 0",
                         "svremap 1, 0, 0, 0, 0, 0, 0",
                         #"setvl 0, 0, 8, 0, 1, 1",
-                        "sv.lwzsh *12, 4(1), 2",  # bit-reversed
+                        "sv.lwz/els *12, 4(1)",
                         #"sv.lwz *12, 0(1)"
                         ])
         lst = list(lst)
@@ -478,7 +479,7 @@ class DecoderTestCase(FHDLTestCase):
                         "sv.stw *5, 0(1)",
                         "svshape 8, 1, 1, 6, 0",
                         "svremap 31, 1, 2, 3, 0, 0, 0",
-                        "sv.lwzsh *12, 4(1), 2"]
+                        "sv.lwz/els *12, 4(1)"]
 
         bitreverse LD is computed as:
         for i in range(VL):
@@ -507,7 +508,7 @@ class DecoderTestCase(FHDLTestCase):
                         "svshape 8, 1, 1, 14, 0",
                         "svremap 16, 0, 0, 0, 0, 0, 0",
                         #"setvl 0, 0, 8, 0, 1, 1",
-                        "sv.lwzsh *12, 4(1), 2",  # bit-reversed
+                        "sv.lwz/els *12, 4(1)",
                         #"sv.lwz *12, 0(1)"
                         ])
         lst = list(lst)