From: lkcl Date: Mon, 19 Sep 2022 22:21:32 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~357 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb9f0ede169a921b07f5348c4b665d513c8292bf;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 67175b5be..cf2e618bf 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -294,8 +294,7 @@ be suitably adapted to each category. It does have to be pointed out that there is huge pressure on the Mode bits. There was therefore insufficient room, unlike the way that EXT001 was designed, to provide "identifying bits" *without first partially -decoding the Suffix*. This should in no way be conflated with the -complexity of a *full* Suffix Decode. +decoding the Suffix*. Some considerable care has been taken to ensure that Decoding may be performed in a strict forward-pipelined fashion that, aside from changes in @@ -328,7 +327,9 @@ Boolean Logic rules on sets (treating the Vector of CR Fields to be tested by tests succeeding (or failing) or whether 'SOME' tests succeed (or fail). These options provide the ability to cover the majority of Parallel 3D GPU Conditions, saving a not inconsiderable number of instructions -especially given the close interaction with CTR in hot-loops. +especially given the close interaction with CTR in hot-loops.[^parity] + +[^parity]: adding a parity (XOR) option was too much. instead a parallel-reduction on `crxor` may be used in combination with a Scalar Branch. Also `SVLR` is introduced, which is a parallel twin of `LR`, and saving and restoring of LR and SVLR may be deferred until the final decision