From: Zachary Snow Date: Thu, 11 Mar 2021 16:49:15 +0000 (-0500) Subject: verilog: disallow overriding global parameters X-Git-Tag: yosys-0.10~257^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cb9f3b6abfbc769589e5e5ceb2497955a155065c;p=yosys.git verilog: disallow overriding global parameters It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters. --- diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index b601d2e25..06e2e23a8 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1286,6 +1286,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump } else { // must be global definition + if ((*it)->type == AST_PARAMETER) + (*it)->type = AST_LOCALPARAM; // cannot be overridden (*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations design->verilog_globals.push_back((*it)->clone()); current_scope.clear(); diff --git a/tests/verilog/global_parameter.ys b/tests/verilog/global_parameter.ys new file mode 100644 index 000000000..a7a3cddc7 --- /dev/null +++ b/tests/verilog/global_parameter.ys @@ -0,0 +1,16 @@ +read_verilog -sv <