From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Sep 2019 05:06:23 +0000 (-0700)
Subject: Oops
X-Git-Tag: working-ls180~1039^2~156
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cba63fe72b27c135e5fe04560d3a625e82c65fe3;p=yosys.git

Oops
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 7bac1b974..d48c646c0 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -192,6 +192,7 @@ void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells)
 		SigSpec Y = lane->getPort("\\Y");
 		A.extend_u0(24, lane->getParam("\\A_SIGNED").as_bool());
 		B.extend_u0(24, lane->getParam("\\B_SIGNED").as_bool());
+		C.append(A);
 		AB.append(B);
 		if (GetSize(Y) < 25)
 			Y.append(module->addWire(NEW_ID, 25-GetSize(Y)));