From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 08:19:34 +0000 (+0100)
Subject: Updating initial state and checks
X-Git-Tag: yosys-0.14~2^2~14
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cbadfa02689ddbd5e9e75324aeb15b2c797d8cc4;p=yosys.git

Updating initial state and checks
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index bea8f12b4..e67f8246b 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1016,22 +1016,35 @@ struct SimWorker : SimShared
 			log_error("Stop time is before start time\n");
 		}
 		auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
-		fst->reconstructAllAtTimes(edges);
-		bool initial = false;
-		for(auto &time : edges) {
-			for(auto &item : inputs) {
-				std::string v = fst->valueAt(item.second, time);
-				top->set_state(item.first, Const::from_string(v));
-			}
-			if (!initial) {
-				top->setInitState(time);
-				initial = true;
+		
+		if ((startCount == stopCount) && writeback) {
+			log("Update initial state with values from %zu\n",startCount);
+			if (edges.empty())
+				edges.push_back(startCount);
+			fst->reconstructAllAtTimes(edges);
+			top->setInitState(startCount);
+			pool<Module*> wbmods;
+			top->writeback(wbmods);
+		} else {
+			if (edges.empty())
+				log_error("No clock edges found in given time range\n");
+			fst->reconstructAllAtTimes(edges);
+			bool initial = false;
+			for(auto &time : edges) {
+				for(auto &item : inputs) {
+					std::string v = fst->valueAt(item.second, time);
+					top->set_state(item.first, Const::from_string(v));
+				}
+				if (!initial) {
+					top->setInitState(time);
+					initial = true;
+				}
+				update();
+
+				bool status = top->checkSignals(time);
+				if (status)
+					log_error("Signal difference at %zu\n", time);
 			}
-			update();
-			
-			bool status = top->checkSignals(time);
-			if (status)
-				log_error("Signal difference at %zu\n", time);
 		}
 	}
 };