From: Florent Kermarrec Date: Tue, 23 Sep 2014 12:11:14 +0000 (+0200) Subject: add dict for fbdiv computation on GTXE2_COMMON X-Git-Tag: 24jan2021_ls180~2572^2~212 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cbbbf8de8b2326f411f7d7a6353c774308915df7;p=litex.git add dict for fbdiv computation on GTXE2_COMMON --- diff --git a/lib/sata/k7satagtx.py b/lib/sata/k7satagtx.py index 44c0a520..102169a1 100644 --- a/lib/sata/k7satagtx.py +++ b/lib/sata/k7satagtx.py @@ -125,17 +125,17 @@ class GTXE2_CHANNEL(Module): # startup config div_config = { - "SATA_I" : 4, - "SATA_II": 2, - "SATA_III": 1 + "SATA_I" : 4, + "SATA_II" : 2, + "SATA_III" : 1 } rxout_div = div_config[start_speed] txout_div = div_config[start_speed] cdr_config = { - "SATA_I" : 0x0380008BFF40100008 - "SATA_II": 0x0380008BFF40200008 - "SATA_III": 0X0380008BFF20200010 + "SATA_I" : 0x0380008BFF40100008 + "SATA_II" : 0x0380008BFF40200008 + "SATA_III" : 0X0380008BFF20200010 } rxcdr_cfg = cdr_config[start_speed] @@ -776,7 +776,7 @@ class GTXE2_CHANNEL(Module): ) class GTXE2_COMMON(Module): - def __init__(self, fbdiv_in, fb_div_ratio): + def __init__(self, fbdiv): self.drp = DRP() self.refclk0 = Signal() @@ -785,6 +785,31 @@ class GTXE2_COMMON(Module): self.qplloutclk = Signal() self.qplloutrefclk = Signal() + # fbdiv config + fbdiv_in_config = { + 16 : 0b0000100000, + 20 : 0b0000110000, + 32 : 0b0001100000, + 40 : 0b0010000000, + 64 : 0b0011100000, + 66 : 0b0101000000, + 80 : 0b0100100000, + 100 : 0b0101110000 + } + fbdiv_in = fbdiv_in_config[fbdiv] + + fbdiv_ratio_config = { + 16 : 0b1, + 20 : 0b1, + 32 : 0b1, + 40 : 0b1, + 64 : 0b1, + 66 : 0b0, + 80 : 0b1, + 100 : 0b1 + } + fbdiv_ratio = fbdiv_ratio_config[fbdiv] + self.specials += \ Instance("GTXE2_COMMON", # Simulation attributes diff --git a/lib/sata/k7sataphy.py b/lib/sata/k7sataphy.py index ba3851ba..d40bfb53 100644 --- a/lib/sata/k7sataphy.py +++ b/lib/sata/k7sataphy.py @@ -5,4 +5,4 @@ from lib.sata import GTXE2_CHANNEL, GTXE2_COMMON class K7SATAPHY(Module): def __init__(self, pads): self.submodules.gtxe2_channel = GTXE2_CHANNEL(pads, "SATA_III") - self.submodules.gtxe2_common = GTXE2_COMMON(0, 0) + self.submodules.gtxe2_common = GTXE2_COMMON(16)