From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 12:47:23 +0000 (+0200)
Subject: Added RTLIL::SigSpecConstIterator
X-Git-Tag: yosys-0.4~392
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cbc3a46a9717f0f6e90b20b29c9003c3720a5aa0;p=yosys.git

Added RTLIL::SigSpecConstIterator
---

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 7c69ff64c..4341e0676 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -70,6 +70,7 @@ namespace RTLIL
 	struct SigChunk;
 	struct SigBit;
 	struct SigSpecIterator;
+	struct SigSpecConstIterator;
 	struct SigSpec;
 	struct CaseRule;
 	struct SwitchRule;
@@ -698,6 +699,16 @@ struct RTLIL::SigSpecIterator
 	inline void operator++() { index++; }
 };
 
+struct RTLIL::SigSpecConstIterator
+{
+	const RTLIL::SigSpec *sig_p;
+	int index;
+
+	inline const RTLIL::SigBit &operator*() const;
+	inline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }
+	inline void operator++() { index++; }
+};
+
 struct RTLIL::SigSpec
 {
 private:
@@ -762,6 +773,9 @@ public:
 	inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }
 	inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }
 
+	inline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }
+	inline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }
+
 	void sort();
 	void sort_and_unify();
 
@@ -829,6 +843,10 @@ inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {
 	return (*sig_p)[index];
 }
 
+inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {
+	return (*sig_p)[index];
+}
+
 inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
 	assert(sig.size() == 1 && sig.chunks().size() == 1);
 	*this = SigBit(sig.chunks().front());