From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 10 Feb 2020 16:43:29 +0000 (+0100)
Subject: soc_core: use add_rom
X-Git-Tag: 24jan2021_ls180~677^2~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cbcd953dd77281d6d8610c009bf73146d7ca85be;p=litex.git

soc_core: use add_rom
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 12560f08..25a10d25 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -147,8 +147,7 @@ class SoCCore(LiteXSoC):
 
         # Add integrated ROM
         if integrated_rom_size:
-            self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init)
-            self.register_rom(self.rom.bus, integrated_rom_size)
+            self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init)
 
         # Add integrated SRAM
         if integrated_sram_size: