From: Jean THOMAS Date: Thu, 4 Jun 2020 09:46:38 +0000 (+0200) Subject: More nMigen conversion and fixes X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cbd51ef311637f7328d79cc0c005342c0b84e1e9;p=gram.git More nMigen conversion and fixes --- diff --git a/gram/core/__init__.py b/gram/core/__init__.py index 86aaac6..7f2254f 100644 --- a/gram/core/__init__.py +++ b/gram/core/__init__.py @@ -1,29 +1,40 @@ -from migen import * +from nmigen import * -from litex.soc.interconnect.csr import AutoCSR +from lambdasoc.periph import Peripheral -from litedram.dfii import DFIInjector -from litedram.core.controller import ControllerSettings, LiteDRAMController -from litedram.core.crossbar import LiteDRAMCrossbar +from gram.dfii import DFIInjector +from gram.core.controller import ControllerSettings, gramController +from gram.core.crossbar import gramCrossbar # Core --------------------------------------------------------------------------------------------- -class LiteDRAMCore(Module, AutoCSR): +class gramCore(Peripheral, Elaboratable): def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs): - self.submodules.dfii = DFIInjector( - addressbits = geom_settings.addressbits, - bankbits = geom_settings.bankbits, - nranks = phy.settings.nranks, - databits = phy.settings.dfi_databits, - nphases = phy.settings.nphases) - self.comb += self.dfii.master.connect(phy.dfi) - - self.submodules.controller = controller = LiteDRAMController( - phy_settings = phy.settings, - geom_settings = geom_settings, - timing_settings = timing_settings, - clk_freq = clk_freq, - **kwargs) - self.comb += controller.dfi.connect(self.dfii.slave) - - self.submodules.crossbar = LiteDRAMCrossbar(controller.interface) + self._phy = phy + self._geom_settings = geom_settings + self._timing_settings = timing_settings + self._clk_freq = clk_freq + self._kwargs = kwargs + + def elaborate(self, platform): + m = Module() + + m.submodules.dfii = DFIInjector( + addressbits = self._geom_settings.addressbits, + bankbits = self._geom_settings.bankbits, + nranks = self._phy.settings.nranks, + databits = self._phy.settings.dfi_databits, + nphases = self._phy.settings.nphases) + m.d.comb += self.dfii.master.connect(self._phy.dfi) + + m.submodules.controller = controller = gramController( + phy_settings = self._phy.settings, + geom_settings = self._geom_settings, + timing_settings = self._timing_settings, + clk_freq = self._clk_freq, + **self._kwargs) + m.d.comb += controller.dfi.connect(self.dfii.slave) + + m.submodules.crossbar = LiteDRAMCrossbar(controller.interface) + + return m diff --git a/gram/core/controller.py b/gram/core/controller.py index 7e6719d..5ef23cc 100644 --- a/gram/core/controller.py +++ b/gram/core/controller.py @@ -43,7 +43,7 @@ class ControllerSettings(Settings): # Controller --------------------------------------------------------------------------------------- -class LiteDRAMController(Module): +class gramController(Elaboratable): def __init__(self, phy_settings, geom_settings, timing_settings, clk_freq, controller_settings=ControllerSettings()): address_align = log2_int(burst_lengths[phy_settings.memtype]) @@ -68,10 +68,11 @@ class LiteDRAMController(Module): databits = phy_settings.dfi_databits, nphases = phy_settings.nphases) - # # # + def elaborate(self, platform): + m = Module() # Refresher -------------------------------------------------------------------------------- - self.submodules.refresher = self.settings.refresh_cls(self.settings, + m.submodules.refresher = self.settings.refresh_cls(self.settings, clk_freq = clk_freq, zqcs_freq = self.settings.refresh_zqcs_freq, postponing = self.settings.refresh_postponing) @@ -85,16 +86,18 @@ class LiteDRAMController(Module): nranks = nranks, settings = self.settings) bank_machines.append(bank_machine) - self.submodules += bank_machine - self.comb += getattr(interface, "bank"+str(n)).connect(bank_machine.req) + m.submodules += bank_machine + m.d.comb += getattr(interface, "bank"+str(n)).connect(bank_machine.req) # Multiplexer ------------------------------------------------------------------------------ - self.submodules.multiplexer = Multiplexer( + m.submodules.multiplexer = Multiplexer( settings = self.settings, bank_machines = bank_machines, refresher = self.refresher, dfi = self.dfi, interface = interface) + return m + def get_csrs(self): return self.multiplexer.get_csrs() diff --git a/gram/core/crossbar.py b/gram/core/crossbar.py index 81200b5..e71650f 100644 --- a/gram/core/crossbar.py +++ b/gram/core/crossbar.py @@ -19,7 +19,7 @@ import gram.stream as stream # LiteDRAMCrossbar --------------------------------------------------------------------------------- -class LiteDRAMCrossbar(Module): +class gramCrossbar(Module): """Multiplexes LiteDRAMController (slave) between ports (masters) To get a port to LiteDRAM, use the `get_port` method. It handles data width diff --git a/gram/modules.py b/gram/modules.py index fa909f4..0397350 100644 --- a/gram/modules.py +++ b/gram/modules.py @@ -15,7 +15,7 @@ from math import ceil from collections import namedtuple -from nmigen import * +from nmigen.utils import log2_int from gram.common import Settings, GeomSettings, TimingSettings diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 70f1672..1070685 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -54,7 +54,7 @@ class ECP5DDRPHYInit(Elaboratable): lock_d = Signal() m.submodules += FFSynchronizer(_lock, lock) m.d.sync += lock_d.eq(lock) - m.d.syn += new_lock.eq(lock & ~lock_d) + m.d.sync += new_lock.eq(lock & ~lock_d) # DDRDLLA/DDQBUFM/ECLK initialization sequence --------------------------------------------- t = 8 # in cycles @@ -95,7 +95,6 @@ class ECP5DDRPHY(Peripheral, Elaboratable): self._sys_clk_freq = sys_clk_freq databits = len(self.pads.dq.o) - print("databits = ", databits) assert databits%8 == 0 # CSR