From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 28 May 2023 22:04:58 +0000 (+0300)
Subject: svp64: mark RA0 operands; introduce RT0 operand
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cbd786066659d4f943f0806fe5b8c47e099bd0ba;p=binutils-gdb.git

svp64: mark RA0 operands; introduce RT0 operand
---

diff --git a/gas/testsuite/gas/ppc/setvl.d b/gas/testsuite/gas/ppc/setvl.d
index 4518ea32720..902233e44f2 100644
--- a/gas/testsuite/gas/ppc/setvl.d
+++ b/gas/testsuite/gas/ppc/setvl.d
@@ -6,11 +6,11 @@
 
 Disassembly of section \.text:
 0+ <\.text>:
-.*:	(37 00 00 58|58 00 00 37) 	setvl.  r0,r0,1,0,0,0
-.*:	(36 00 00 58|58 00 00 36) 	setvl   r0,r0,1,0,0,0
-.*:	(36 00 e0 5b|5b e0 00 36) 	setvl   r31,r0,1,0,0,0
-.*:	(36 00 1f 58|58 1f 00 36) 	setvl   r0,r31,1,0,0,0
-.*:	(36 7e 00 58|58 00 7e 36) 	setvl   r0,r0,64,0,0,0
-.*:	(76 00 00 58|58 00 00 76) 	setvl   r0,r0,1,1,0,0
-.*:	(b6 00 00 58|58 00 00 b6) 	setvl   r0,r0,1,0,1,0
-.*:	(36 01 00 58|58 00 01 36) 	setvl   r0,r0,1,0,0,1
+.*:	(37 00 00 58|58 00 00 37) 	setvl.  0,0,1,0,0,0
+.*:	(36 00 00 58|58 00 00 36) 	setvl   0,0,1,0,0,0
+.*:	(36 00 e0 5b|5b e0 00 36) 	setvl   r31,0,1,0,0,0
+.*:	(36 00 1f 58|58 1f 00 36) 	setvl   0,r31,1,0,0,0
+.*:	(36 7e 00 58|58 00 7e 36) 	setvl   0,0,64,0,0,0
+.*:	(76 00 00 58|58 00 00 76) 	setvl   0,0,1,1,0,0
+.*:	(b6 00 00 58|58 00 00 b6) 	setvl   0,0,1,0,1,0
+.*:	(36 01 00 58|58 00 01 36) 	setvl   0,0,1,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index ab06775d9ff..e2e141bf1e1 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3465,7 +3465,11 @@ const struct powerpc_operand powerpc_operands[] =
 #define RD RS
   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 
-#define RD_EVEN RS + 1
+  /* As above, but 0 in the RT field means zero, not r0.  */
+#define RT0 RS + 1
+  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
+
+#define RD_EVEN RT0 + 1
 #define RS_EVEN RD_EVEN
   { 0x1f, 21, insert_rD_rS_even, extract_rD_rS_even, PPC_OPERAND_GPR },
 
@@ -6477,24 +6481,24 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"addpcis",  DX(19,2),		DX_MASK,     POWER9,	PPCVLE,		{RT, DXD}},
 {"subpcis",  DX(19,2),		DX_MASK,     POWER9,	PPCVLE|EXT,	{RT, NDXD}},
 
-{"minu",	MMXMMM(19,3,0,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"minu.",	MMXMMM(19,3,0,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"maxu",	MMXMMM(19,3,1,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"maxu.",	MMXMMM(19,3,1,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"mins",	MMXMMM(19,3,2,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"mins.",	MMXMMM(19,3,2,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"maxs",	MMXMMM(19,3,3,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"maxs.",	MMXMMM(19,3,3,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"minuw",	MMXMMM(19,3,4,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"minuw.",	MMXMMM(19,3,4,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"maxuw",	MMXMMM(19,3,5,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"maxuw.",	MMXMMM(19,3,5,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"minsw",	MMXMMM(19,3,6,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"minsw.",	MMXMMM(19,3,6,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"maxsw",	MMXMMM(19,3,7,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"maxsw.",	MMXMMM(19,3,7,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB}},
-{"minmax",	MM(19,3,0),		MM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB, MMM}},
-{"minmax.",	MM(19,3,1),		MM_MASK,	SFFS,	PPCVLE,	{RT, RA, RB, MMM}},
+{"minu",	MMXMMM(19,3,0,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"minu.",	MMXMMM(19,3,0,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"maxu",	MMXMMM(19,3,1,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"maxu.",	MMXMMM(19,3,1,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"mins",	MMXMMM(19,3,2,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"mins.",	MMXMMM(19,3,2,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"maxs",	MMXMMM(19,3,3,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"maxs.",	MMXMMM(19,3,3,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"minuw",	MMXMMM(19,3,4,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"minuw.",	MMXMMM(19,3,4,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"maxuw",	MMXMMM(19,3,5,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"maxuw.",	MMXMMM(19,3,5,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"minsw",	MMXMMM(19,3,6,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"minsw.",	MMXMMM(19,3,6,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"maxsw",	MMXMMM(19,3,7,0),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"maxsw.",	MMXMMM(19,3,7,1),	MMXMMM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB}},
+{"minmax",	MM(19,3,0),		MM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB, MMM}},
+{"minmax.",	MM(19,3,1),		MM_MASK,	SFFS,	PPCVLE,	{RT, RA0, RB, MMM}},
 
 {"bdnzlr-",  XLO(19,BODNZ,16,0),	XLBOBIBB_MASK, PPCCOM,	 ISA_V2|PPCVLE|EXT,	{BH}},
 {"bdnzlr+",  XLO(19,BODNZP,16,0),	XLBOBIBB_MASK, PPCCOM,	 ISA_V2|PPCVLE|EXT,	{BH}},
@@ -7094,8 +7098,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"svshape2",	SVM2(22,281),	SVM2_MASK,	SFFS,	PPCVLE,	{SVo, yx10, rmm, SVd, sk, mm}},
 {"svshape",	SVM(22,25),	SVM_MASK,	SFFS,	PPCVLE,	{SVxd, SVyd, SVzd, SVrm, vf}},
 
-{"setvl",	SVL(22,27,0),	SVL_MASK,	SFFS,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
-{"setvl.",	SVL(22,27,1),	SVL_MASK,	SFFS,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
+{"setvl",	SVL(22,27,0),	SVL_MASK,	SFFS,	PPCVLE,	{RT0, RA0, SVi, vf, vs, ms}},
+{"setvl.",	SVL(22,27,1),	SVL_MASK,	SFFS,	PPCVLE,	{RT0, RA0, SVi, vf, vs, ms}},
 
 {"svindex",	SVI(22,41),	SVI_MASK,	SFFS,	PPCVLE,	{SVG, rmm, SVd, ew, yx, mm, sk}},