From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 May 2021 16:32:26 +0000 (+0100)
Subject: add SVSRR0 to FastRegsEnum
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cbd7e976519c1e53bdd7316acb5ca0feb269bd2d;p=soc.git

add SVSRR0 to FastRegsEnum
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 1f45ab91..26abc779 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -90,7 +90,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
 class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray):
     """FastRegs
 
-    FAST regfile  - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC
+    FAST regfile  - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC, SVSRR0
 
     * QTY 6of 64-bit registers
     * 3R2W