From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 May 2020 15:28:30 +0000 (+0100)
Subject: add some more stub comments
X-Git-Tag: div_pipeline~832
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cbe73194adcd0e47670fc6297ce2bb8995f3f3e5;p=soc.git

add some more stub comments
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index d95389cf..355b78bb 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -379,7 +379,10 @@ def test_compunit():
 
 
 class CompUnitParallelTest:
-    def __init__(self, dut):
+    def __init__(self, dut,
+        # TODO add a, b, expected_o, and other parameters such as imm_mode, zero
+        # operand etc.
+            ):
         self.dut = dut
 
     def driver(self):
@@ -415,10 +418,14 @@ class CompUnitParallelTest:
     def rd(self, rd_idx):
         # monitor self.dut.rd.req[rd_idx] and sets dut.rd.go[idx] for one cycle
         yield
+        # TODO: also when dut.rd.go is set, put the expected value into
+        # the src_i.
 
     def wr(self, wr_idx):
         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
         yield
+        # TODO: also when dut.wr.go is set, check the output against the
+        # self.expected_o and assert
 
 def test_compunit_regspec1():
     from alu_hier import ALU