From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 29 Jul 2020 13:28:33 +0000 (+0200)
Subject: Clear last error message
X-Git-Tag: working-ls180~341^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc02d58194fc6de11f625e670d23cdec814dc366;p=yosys.git

Clear last error message
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 0276618b4..632dc51fd 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2354,8 +2354,10 @@ struct VerificPass : public Pass {
 			while (argidx < GetSize(args))
 				file_names.Insert(args[argidx++].c_str());
 
-			if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU))
+			if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
+					verific_error_msg.clear();
 					log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
+			}
 
 			verific_import_pending = true;
 			goto check_error;