From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 24 May 2013 13:15:59 +0000 (+0200)
Subject: Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
X-Git-Tag: yosys-0.2.0~619
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc0540412832859d28e5c24c8be95c725c10ed19;p=yosys.git

Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
---

diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
index 0097b1c98..2e9448950 100644
--- a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
+++ b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
@@ -4,11 +4,13 @@ reg req_0 , req_1 ,  req_2 , req_3;
 wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
 
 initial begin
+  // $dumpfile("testbench.vcd");
+  // $dumpvars(0, testbench);
   $display("Time\t    R0 R1 R2 R3 G0 G1 G2 G3");
   $monitor("%g\t    %b  %b  %b  %b  %b  %b  %b  %b", 
     $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
   clock = 0;
-  reset = 0;
+  reset = 1;
   req_0 = 0;
   req_1 = 0;
   req_2 = 0;