From: Francisco Jerez Date: Tue, 12 Dec 2017 20:05:02 +0000 (-0800) Subject: intel/ir: Allow representing additional flag subregisters in the IR. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc0fc8b8ac608b036d260007a689eeeb8e815031;p=mesa.git intel/ir: Allow representing additional flag subregisters in the IR. This allows representing conditional mods and predicates on f1.0-f1.1 at the IR level by adding an extra bit to the flag_subreg backend_instruction field. Reviewed-by: Jordan Justen Reviewed-by: Kenneth Graunke --- diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 0d7988dae47..16b6a06c69d 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -5488,9 +5488,10 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) fs_inst *inst = (fs_inst *)be_inst; if (inst->predicate) { - fprintf(file, "(%cf0.%d) ", - inst->predicate_inverse ? '-' : '+', - inst->flag_subreg); + fprintf(file, "(%cf%d.%d) ", + inst->predicate_inverse ? '-' : '+', + inst->flag_subreg / 2, + inst->flag_subreg % 2); } fprintf(file, "%s", brw_instruction_name(devinfo, inst->opcode)); @@ -5502,7 +5503,8 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL && inst->opcode != BRW_OPCODE_IF && inst->opcode != BRW_OPCODE_WHILE))) { - fprintf(file, ".f0.%d", inst->flag_subreg); + fprintf(file, ".f%d.%d", inst->flag_subreg / 2, + inst->flag_subreg % 2); } } fprintf(file, "(%d) ", inst->exec_size); @@ -5888,7 +5890,7 @@ fs_visitor::calculate_register_pressure() bool fs_visitor::opt_drop_redundant_mov_to_flags() { - bool flag_mov_found[2] = {false}; + bool flag_mov_found[4] = {false}; bool progress = false; /* Instructions removed by this pass can only be added if this were true */ diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index a5a821a13b0..557b098c207 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -1508,7 +1508,7 @@ fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst, void fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst) { - struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg); + struct brw_reg flags = brw_flag_subreg(inst->flag_subreg); struct brw_reg dispatch_mask; if (devinfo->gen >= 6) @@ -1764,7 +1764,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) brw_set_default_access_mode(p, BRW_ALIGN_1); brw_set_default_predicate_control(p, inst->predicate); brw_set_default_predicate_inverse(p, inst->predicate_inverse); - brw_set_default_flag_reg(p, 0, inst->flag_subreg); + brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2); brw_set_default_saturate(p, inst->saturate); brw_set_default_mask_control(p, inst->force_writemask_all); brw_set_default_acc_write_control(p, inst->writes_accumulator); diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index 17d5b97bf31..c41408104fa 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -842,6 +842,13 @@ brw_flag_reg(int reg, int subreg) BRW_ARF_FLAG + reg, subreg); } +static inline struct brw_reg +brw_flag_subreg(unsigned subreg) +{ + return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, + BRW_ARF_FLAG + subreg / 2, subreg % 2); +} + /** * Return the mask register present in Gen4-5, or the related register present * in Gen7.5 and later hardware referred to as "channel enable" register in diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index 692f7125323..0e793de4ddf 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -974,7 +974,7 @@ fs_instruction_scheduler::calculate_deps() */ schedule_node *last_grf_write[grf_count * 16]; schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->gen)]; - schedule_node *last_conditional_mod[4] = {}; + schedule_node *last_conditional_mod[8] = {}; schedule_node *last_accumulator_write = NULL; /* Fixed HW registers are assumed to be separate from the virtual * GRFs, so they can be tracked separately. We don't really write diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h index 06abdc4d175..fd02feb9107 100644 --- a/src/intel/compiler/brw_shader.h +++ b/src/intel/compiler/brw_shader.h @@ -169,10 +169,10 @@ struct backend_instruction { bool shadow_compare:1; bool eot:1; - /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional + /* Chooses which flag subregister (f0.0 to f1.1) is used for conditional * mod and predication. */ - unsigned flag_subreg:1; + unsigned flag_subreg:2; /** The number of hardware registers used for a message header. */ uint8_t header_size; diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index e95886349d8..82052b9bad7 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -1542,9 +1542,10 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) vec4_instruction *inst = (vec4_instruction *)be_inst; if (inst->predicate) { - fprintf(file, "(%cf0.%d%s) ", + fprintf(file, "(%cf%d.%d%s) ", inst->predicate_inverse ? '-' : '+', - inst->flag_subreg, + inst->flag_subreg / 2, + inst->flag_subreg % 2, pred_ctrl_align16[inst->predicate]); } @@ -1558,7 +1559,7 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL && inst->opcode != BRW_OPCODE_IF && inst->opcode != BRW_OPCODE_WHILE))) { - fprintf(file, ".f0.%d", inst->flag_subreg); + fprintf(file, ".f%d.%d", inst->flag_subreg / 2, inst->flag_subreg % 2); } } fprintf(file, " "); diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index f5d6ad8e483..6fa6e35b24a 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -1517,7 +1517,7 @@ generate_code(struct brw_codegen *p, brw_set_default_predicate_control(p, inst->predicate); brw_set_default_predicate_inverse(p, inst->predicate_inverse); - brw_set_default_flag_reg(p, 0, inst->flag_subreg); + brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2); brw_set_default_saturate(p, inst->saturate); brw_set_default_mask_control(p, inst->force_writemask_all); brw_set_default_acc_write_control(p, inst->writes_accumulator);