From: Lionel Landwerlin Date: Sun, 2 Feb 2020 13:25:16 +0000 (+0100) Subject: intel/genxml: add PIPE_CONTROL command cache invalidate bit X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc13bfbd05934f4053b633627f5bd2ef1108537b;p=mesa.git intel/genxml: add PIPE_CONTROL command cache invalidate bit This new bit invalidates the cache/prefetch of commands in the command streamer. This will be useful for self modifying batches. Signed-off-by: Lionel Landwerlin Reviewed-by: Jason Ekstrand Part-of: --- diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index d778abcbfed..5e87d5affc2 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -6272,6 +6272,7 @@ + diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index f5ccb182681..b8bada119c2 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -6413,6 +6413,7 @@ +