From: lkcl <lkcl@web>
Date: Thu, 13 Oct 2022 00:29:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~81
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc14973786538d535f3289a5d3626f67cb4275ef;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index c1bb830c7..2ee6bfea5 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -418,8 +418,6 @@ is based on whether the number of src operands is 2 or 3.  With only
 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
-* `RM-2P-1S1D-PU` Twin Predication (src=1, dest=1) with Pack/Unpack,
-   primarily for LDST (Immediate)' mv and swizzle mv
 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update