From: lkcl <lkcl@web>
Date: Fri, 25 Dec 2020 18:02:33 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~894
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc14bcbd7a015806c3bcd15ee725ab78ba9aafde;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 92a7b7679..bbef5ae5b 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -505,3 +505,19 @@ With VL truncated the analysis looking for the zero byte and the subsequent STOR
 
 SIMD strncpy hand-written assembly routines are, to be blunt about it, a total nightmare.  240 instructions is not uncommon, and the worst thing about them is that they are unable to cope with detection of a page fault condition.
 
+# Data-dependent fail-first
+
+This is a minor variant on the CR-based predicate-result mode.  Where ored-result continues with independent element testing, data-dependent fail-first *stops* at the first failure:
+
+    for i in range(VL):
+        # predication test, skip all masked out elements.
+        if predicate_masked_out(i): continue # skip
+        result = op(iregs[RA+i], iregs[RB+i])
+        CRnew = analyse(result) # calculates eq/lt/gt
+        # now test CR, similar to branch
+        if CRnew[BO[0:1]] != BO[2]:
+            VL = i # truncate: only successes allowed
+            break
+        # test passed: store result (and CR?)
+        iregs[RT+i] = result
+        if Rc=1: crregs[offs+i] = CRnew