From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 31 May 2020 17:03:31 +0000 (+0100)
Subject: add comments for MultiCompUnit parallel test
X-Git-Tag: div_pipeline~710
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc17998e15db9ee22738fa37c6dc8f943c812ab7;p=soc.git

add comments for MultiCompUnit parallel test
---

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index f794ad98..71b592a4 100644
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -224,6 +224,11 @@ class CompUnitParallelTest:
               "it's because the above test unexpectedly passed.")
 
     def rd(self, rd_idx):
+        # TODO: rdmaskn (inverted-rdmask) now needs to be included, here.
+        # any bit in rdmaskn, if set, indicates that the corresponding bit
+        # in rd.rel must *not* be activated (never go HI).  likewise, the
+        # corresponding rd.go bit should never be raised
+
         # wait for issue_i to rise
         while True:
             issue_i = yield self.dut.issue_i