From: Jeff Wang <jjj11x@gmail.com>
Date: Thu, 16 Jan 2020 22:11:08 +0000 (-0500)
Subject: lexer doesn't seem to return TOK_REG for logic anymore
X-Git-Tag: working-ls180~791^2~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc2236d0c02be096ad1b92209072be3f16598933;p=yosys.git

lexer doesn't seem to return TOK_REG for logic anymore
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 08db36276..ea0a09599 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1261,13 +1261,14 @@ enum_type: TOK_ENUM {
 
 enum_base_type: int_vec param_range
 	| int_atom
-	| /* nothing */		{ addRange(astbuf1); }
+	| /* nothing */		{astbuf1->is_reg = true; addRange(astbuf1); }
 	;
 
-int_atom: TOK_INTEGER		{ addRange(astbuf1); }		// probably should do byte, range [7:0] here
+int_atom: TOK_INTEGER		{astbuf1->is_reg=true; addRange(astbuf1); }		// probably should do byte, range [7:0] here
 	;
 
-int_vec: TOK_REG		{ astbuf1->is_reg = true; }	// lexer returns this for logic|bit too
+int_vec: TOK_REG {astbuf1->is_reg = true;}
+	| TOK_LOGIC  {astbuf1->is_logic = true;}
 	;
 
 enum_name_list: