From: Luke Kenneth Casson Leighton Date: Mon, 16 Apr 2018 02:27:23 +0000 (+0100) Subject: add SIMD section X-Git-Tag: convert-csv-opcode-to-binary~5661 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc2d35f42996251d67db90089ff28ef0adb88044;p=libreriscv.git add SIMD section --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index d5adea1c6..8dc72630b 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -1109,8 +1109,8 @@ with minimum disruption and effort. even an in-order single-issue implementation with a single ALU would still appear to have parallel vectoristion. * hard-to-judge: if actual inherent underlying ALU parallelism is added it's - hard to say if there would be pluses or minuses. At worse it would - be "no worse" than existing register renaming, OoO, VLIW and register + hard to say if there would be pluses or minuses (on die area). At worse it + would be "no worse" than existing register renaming, OoO, VLIW and register file cacheing schemes. ## RVV (as it stands, Draft 0.4 Section 17, RISC-V ISA V2.3-Draft)