From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 23:27:07 +0000 (-0700)
Subject: Add test
X-Git-Tag: working-ls180~1160^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc331cf70d9e9f7095e335fc217fd3dbbbe92a93;p=yosys.git

Add test
---

diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index 160c767fb..7e928ec78 100644
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -1,6 +1,5 @@
 read_verilog test_arith.v
 synth_ice40
-techmap -map ../cells_sim.v
 rename test gate
 
 read_verilog test_arith.v
@@ -8,3 +7,13 @@ rename test gold
 
 miter -equiv -flatten -make_outputs gold gate miter
 sat -verify -prove trigger 0 -show-ports miter
+
+delete A:whitebox # Necessary since whiteboxes cannot
+                  # be overwritten...
+synth_ice40 -top gate
+
+read_verilog test_arith.v
+rename test gold
+
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 -show-ports miter