From: William D. Jones <thor0505@comcast.net>
Date: Sat, 21 Nov 2020 02:24:39 +0000 (-0500)
Subject: machxo2: Improve FACADE_FF simulation model.
X-Git-Tag: working-ls180~66
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc52eb53cde6863ae209343c234c33e1092e94b6;p=yosys.git

machxo2: Improve FACADE_FF simulation model.
---

diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v
index 2c4d2f462..8d93a4a33 100644
--- a/techlibs/machxo2/cells_sim.v
+++ b/techlibs/machxo2/cells_sim.v
@@ -24,7 +24,8 @@ module FACADE_FF #(
 	parameter LSRMUX = "LSR",
 	parameter LSRONMUX = "LSRMUX",
 	parameter SRMODE = "LSR_OVER_CE",
-	parameter REGSET = "SET"
+	parameter REGSET = "SET",
+	parameter REGMODE = "FF"
 ) (
 	input CLK, DI, LSR, CE,
 	output reg Q
@@ -41,22 +42,29 @@ module FACADE_FF #(
 	endgenerate
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
+	wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
 	wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 
 	generate
-		if (SRMODE == "ASYNC") begin
-			always @(posedge muxclk, posedge muxlsr)
-				if (muxlsr)
-					Q <= srval;
-				else if (muxce)
-					Q <= DI;
+		if (REGMODE == "FF") begin
+			if (SRMODE == "ASYNC") begin
+				always @(posedge muxclk, posedge muxlsron)
+					if (muxlsron)
+						Q <= srval;
+					else if (muxce)
+						Q <= DI;
+			end else begin
+				always @(posedge muxclk)
+					if (muxlsron)
+						Q <= srval;
+					else if (muxce)
+						Q <= DI;
+			end
+		end else if (REGMODE == "LATCH") begin
+			ERROR_UNSUPPORTED_FF_MODE error();
 		end else begin
-			always @(posedge muxclk)
-				if (muxlsr)
-					Q <= srval;
-				else if (muxce)
-					Q <= DI;
+			ERROR_UNKNOWN_FF_MODE error();
 		end
 	endgenerate
 endmodule