From: Connor Abbott <cwabbott0@gmail.com>
Date: Wed, 22 Apr 2020 13:04:25 +0000 (+0200)
Subject: freedreno/a6xx: Document PrimID passthrough registers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc530858c1e6adb761fca163f49432fbc71348b9;p=mesa.git

freedreno/a6xx: Document PrimID passthrough registers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4704>
---

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 2402395fa51..ce46a08dad8 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -2559,7 +2559,10 @@ to upconvert to 32b float internally?
 
 	<reg32 offset="0x9304" name="VPC_CNTL_0">
 		<bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
+		<!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
+		<bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
 		<bitfield name="VARYING" pos="16" type="boolean"/>
+		<bitfield name="UNKLOC" low="24" high="31" type="uint"/>
 	</reg32>
 
 	<reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
@@ -2607,7 +2610,11 @@ to upconvert to 32b float internally?
 
 	<!-- always 0x1 ? -->
 	<reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
-	<reg32 offset="0x9806" name="PC_UNKNOWN_9806"/>
+
+	<!-- probably a mirror of VFD_CONTROL_6 -->
+	<reg32 offset="0x9806" name="PC_PRIMID_CNTL">
+		<bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
+	</reg32>
 
 	<reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
 	<reg32 offset="0x9981" name="PC_UNKNOWN_9981"/>
@@ -2721,6 +2728,12 @@ to upconvert to 32b float internally?
 		<bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
 	</reg32>
 	<reg32 offset="0xa006" name="VFD_CONTROL_6">
+		<!--
+			True if gl_PrimitiveID is read via the FS and there is
+			no matching write from the GS, and therefore it needs to
+			be passed through via fixed-function logic.
+		-->
+		<bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
 	</reg32>
 
 	<reg32 offset="0xa007" name="VFD_MODE_CNTL">
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index 10577c75985..76b92062907 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -821,7 +821,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
                         A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
-   tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
+   tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMID_CNTL, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
 
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 024b139d130..59c2d15a266 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -1302,7 +1302,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
 
 	WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 
-	WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
+	WRITE(REG_A6XX_PC_PRIMID_CNTL, 0);
 	WRITE(REG_A6XX_PC_UNKNOWN_9990, 0);
 	WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);