From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Sat, 5 Mar 2016 01:56:12 +0000 (-0800)
Subject: anv/pipeline: Fix depthBiasEnable on gen7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc57efc67abb5b81ebc2648775d8829ab27b7df8;p=mesa.git

anv/pipeline: Fix depthBiasEnable on gen7

The first time I tried to fix this, I set the wrong fields.
---

diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index d563a8c26cd..5235d399ce5 100644
--- a/src/intel/vulkan/gen7_pipeline.c
+++ b/src/intel/vulkan/gen7_pipeline.c
@@ -67,9 +67,9 @@ gen7_emit_rs_state(struct anv_pipeline *pipeline,
       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
       .UsePointWidthState                       = !pipeline->writes_point_size,
       .PointWidth                               = 1.0,
-      .GlobalDepthOffsetConstant                = info->depthBiasEnable,
-      .GlobalDepthOffsetScale                   = info->depthBiasEnable,
-      .GlobalDepthOffsetClamp                   = info->depthBiasEnable,
+      .GlobalDepthOffsetEnableSolid             = info->depthBiasEnable,
+      .GlobalDepthOffsetEnableWireframe         = info->depthBiasEnable,
+      .GlobalDepthOffsetEnablePoint             = info->depthBiasEnable,
    };
 
    GENX(3DSTATE_SF_pack)(NULL, &pipeline->gen7.sf, &sf);