From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 30 Jul 2020 14:12:05 +0000 (+0100)
Subject: core_start/stop/endian were inverted (output)
X-Git-Tag: semi_working_ecp5~484
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc9239c1236bb9685fb57903a0ecee589199483e;p=soc.git

core_start/stop/endian were inverted (output)
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index c45bb28a..854a5e66 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -74,9 +74,9 @@ class TestIssuer(Elaboratable):
         # busy/halted signals from core
         comb += self.busy_o.eq(core.busy_o)
         comb += self.halted_o.eq(core.core_terminated_o)
-        comb += self.core_start_i.eq(core.core_start_i)
-        comb += self.core_stop_i.eq(core.core_stop_i)
-        comb += self.core_bigendian_i.eq(core.bigendian_i)
+        comb += core.core_start_i.eq(self.core_start_i)
+        comb += core.core_stop_i.eq(self.core_stop_i)
+        comb += core.bigendian_i.eq(self.core_bigendian_i)
 
         # temporary hack: says "go" immediately for both address gen and ST
         l0 = core.l0