From: lkcl <lkcl@web>
Date: Sun, 4 Sep 2022 12:31:22 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~707
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cc9f0da7071fe816354bae0a67c2fae66e92fc5a;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index caa65ae0b..2b430f931 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -88,9 +88,11 @@ Comparative instruction count:
   AVX-128 and AVX-256 which in turn critically rely on the rest of
   x86, for a grand total of well over 10,000 instructions.
 * RISV-V RVV: 192 instructions, prerequisite 96 Scalar RV64GC instructions
-* SVP64: **five** instructions, 24-bit prefixing of
+* SVP64: **six** instructions, two of which are in the same space
+  (svshape, svshape2), with 24-bit prefixing of
   prerequisite SFS (150) or
-  SFFS (214) Compliancy Subsets
+  SFFS (214) Compliancy Subsets.
+  **There are no dedicated Vector instructions, only Scalar-prefixed**.
 
 SV comprises several [[sv/compliancy_levels]] suited to Embedded, Energy
 efficient High-Performance Compute, Distributed Computing and Advanced
@@ -137,7 +139,7 @@ Core SVP64 instructions:
   Vertical-First Mode and also providing traditional "Vector Iota"
   capability.
 
-*Please note: there are only five instructions in the whole of SV.
+*Please note: there are only six instructions in the whole of SV.
 Beyond this point are additional **Scalar** instructions related to
 specific workloads that have nothing to do with the SV Specification*