From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Jun 2020 11:33:38 +0000 (+0100)
Subject: ilang file output change from alu_pipeline.il to div_pipeline.il
X-Git-Tag: div_pipeline~433
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cca0653285271f948dcd05640628f1a82c73ec37;p=soc.git

ilang file output change from alu_pipeline.il to div_pipeline.il
---

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 2e66f90a..4a25a5fa 100644
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -190,7 +190,7 @@ class DIVTestCase(FHDLTestCase):
         pspec = DIVPipeSpec(id_wid=2)
         alu = DIVBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
-        with open("alu_pipeline.il", "w") as f:
+        with open("div_pipeline.il", "w") as f:
             f.write(vl)