From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Thu, 9 Jul 2020 13:08:30 +0000 (+0200)
Subject: Add test for SoC readout
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cca815b0861d56e8705d0a074b9717123e745a09;p=gram.git

Add test for SoC readout
---

diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index 0f33a65..3813bf4 100644
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -1,6 +1,7 @@
 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
 
 from nmigen import *
+from nmigen.asserts import Assert, Assume
 from nmigen_soc import wishbone, memory
 from nmigen.lib.cdc import ResetSynchronizer
 
@@ -99,7 +100,55 @@ class SocTestCase(FHDLTestCase):
         m.submodules += soc
 
         def process():
-            #res = yield from wb_read(soc.bus, 0x10000000 >> 2, 0xF, 16384)
-            yield
+            yield from wb_write(soc.bus, 0x0, 0xE, 0xF) # DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE
+            yield from wb_write(soc.bus, 0xC >> 2, 0x0, 0xF)
+            yield from wb_write(soc.bus, 0x10 >> 2, 0x0, 0xF)
+            yield from wb_write(soc.bus, 0x0, 0xC, 0xF)
+
+            yield from wb_write(soc.bus, 0x0, 0xE, 0xF)
+
+            # MR2
+            yield from wb_write(soc.bus, 0xC >> 2, 0x200, 0xF)
+            yield from wb_write(soc.bus, 0x10 >> 2, 0x2, 0xF)
+            yield from wb_write(soc.bus, 0x4 >> 2, 0xF, 0xF)
+            yield from wb_write(soc.bus, 0x8 >> 2, 0x1, 0xF)
+
+            # MR3
+            yield from wb_write(soc.bus, 0xC >> 2, 0x0, 0xF)
+            yield from wb_write(soc.bus, 0x10 >> 2, 0x3, 0xF)
+            yield from wb_write(soc.bus, 0x4 >> 2, 0xF, 0xF)
+            yield from wb_write(soc.bus, 0x8 >> 2, 0x1, 0xF)
+
+            # MR1
+            yield from wb_write(soc.bus, 0xC >> 2, 0x6, 0xF)
+            yield from wb_write(soc.bus, 0x10 >> 2, 0x1, 0xF)
+            yield from wb_write(soc.bus, 0x4 >> 2, 0xF, 0xF)
+            yield from wb_write(soc.bus, 0x8 >> 2, 0x1, 0xF)
+
+            # MR0
+            yield from wb_write(soc.bus, 0xC >> 2, 0x320, 0xF)
+            yield from wb_write(soc.bus, 0x10 >> 2, 0x0, 0xF)
+            yield from wb_write(soc.bus, 0x4 >> 2, 0xF, 0xF)
+            yield from wb_write(soc.bus, 0x8 >> 2, 0x1, 0xF)
+
+            for i in range(200):
+                yield
+
+            # ZQ
+            yield from wb_write(soc.bus, 0xC >> 2, 0x400, 0xF)
+            yield from wb_write(soc.bus, 0x10 >> 2, 0x0, 0xF)
+            yield from wb_write(soc.bus, 0x4 >> 2, 0x3, 0xF)
+            yield from wb_write(soc.bus, 0x8 >> 2, 0x1, 0xF)
+
+            for i in range(200):
+                yield
+
+            yield from wb_write(soc.bus, 0, 0x1, 0xF)
+
+            for i in range(2000):
+                yield
+
+            res = yield from wb_read(soc.bus, 0x10000000 >> 2, 0xF, 16384)
+            self.assertEqual(res, 0xDEADBEEF)
 
         runSimulation(m, process, "test_soc.vcd")