From: whitequark <cz@m-labs.hk>
Date: Sat, 29 Dec 2018 15:02:44 +0000 (+0000)
Subject: lib.cdc: fix tests to actually run.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ccc058d8c4b5fd0a18abfaa9f5f58ad4f2cec1b5;p=nmigen.git

lib.cdc: fix tests to actually run.
---

diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py
index 462a422..7ee588d 100644
--- a/nmigen/hdl/ast.py
+++ b/nmigen/hdl/ast.py
@@ -860,7 +860,7 @@ class Delay(Statement):
 
 
 class Tick(Statement):
-    def __init__(self, domain):
+    def __init__(self, domain="sync"):
         self.domain = str(domain)
 
     def _rhs_signals(self):
diff --git a/nmigen/test/test_lib_cdc.py b/nmigen/test/test_lib_cdc.py
index b65c04e..af68d2f 100644
--- a/nmigen/test/test_lib_cdc.py
+++ b/nmigen/test/test_lib_cdc.py
@@ -21,6 +21,7 @@ class MultiRegTestCase(FHDLTestCase):
                 yield Tick()
                 self.assertEqual((yield o), 1)
             sim.add_process(process)
+            sim.run()
 
     def test_basic(self):
         i = Signal(reset=1)
@@ -38,3 +39,4 @@ class MultiRegTestCase(FHDLTestCase):
                 yield Tick()
                 self.assertEqual((yield o), 0)
             sim.add_process(process)
+            sim.run()