From: Luke Kenneth Casson Leighton Date: Fri, 9 Sep 2022 01:12:40 +0000 (+0100) Subject: clarify X-Git-Tag: opf_rfc_ls005_v1~571 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ccd4c70cc03a3914c23f859d49a8e3df2ab2d820;p=libreriscv.git clarify --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index aeae7e8ae..babc49455 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -118,8 +118,8 @@ such large numbers of registers, even for Multi-Issue microarchitectures. currently named "SVP64-Single" [^likeext001] * A third 24-bits (third 2-bit XO) is strongly recommended to be **reserved** such that future unforeseen capability is needed. -* To hold all Vector Context, five SPRs are needed for userspace - (MSR.PR=1 Problem State). If Supervisor and Hypervisor mode are to +* To hold all Vector Context, five SPRs are needed for userspace. + If Supervisor and Hypervisor mode are to also support Simple-V they will correspondingly need five SPRs each. * Five 6-bit XO (A-Form) "Management" instructions are needed. These are Scalar 32-bit instructions and *may* be 64-bit-extended in future