From: lkcl <lkcl@web>
Date: Mon, 3 Oct 2022 15:25:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~229
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cce042a59aa5a84c86afe913d2b7c5b1458bad9d;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 788c74e04..7900070e1 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -290,6 +290,10 @@ Indexed LD is:
         if (RB.isvec) k++;
         if (RT.isvec) j++;
 
+Note that Element-Strided uses the Destination Step because with both
+sources being Scalar as a prerequisite condition of activation of
+Element-Stride Mode, the source step (being Scalar) would never advance.
+
 Note in both cases that [[sv/svp64]] allows RA-as-a-dest in "update" mode (`ldux`) to be effectively a *completely different* register from RA-as-a-source.  This because there is room in svp64 to extend RA-as-src as well as RA-as-dest, both independently as scalar or vector *and* independently extending their range.
 
 *Programmer's note: being able to set RA-as-a-source