From: Jerome Glisse <jglisse@redhat.com>
Date: Thu, 24 Jul 2014 21:30:31 +0000 (-0400)
Subject: winsys/radeon: fix indentation
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cce58147eb1450a26c03756af37da52d180580c4;p=mesa.git

winsys/radeon: fix indentation

Can we please keep it clean and avoid ending up in messy situation
like ddx.

Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
---

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 3596f8d1cd0..a06ecb203f2 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -155,7 +155,7 @@ static struct radeon_winsys_cs *
 radeon_drm_cs_create(struct radeon_winsys *rws,
                      enum ring_type ring_type,
                      void (*flush)(void *ctx, unsigned flags,
-				   struct pipe_fence_handle **fence),
+                                   struct pipe_fence_handle **fence),
                      void *flush_ctx,
                      struct radeon_winsys_cs_handle *trace_buf)
 {
@@ -196,10 +196,10 @@ radeon_drm_cs_create(struct radeon_winsys *rws,
 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 
 static INLINE void update_reloc(struct drm_radeon_cs_reloc *reloc,
-				enum radeon_bo_domain rd,
-				enum radeon_bo_domain wd,
-				unsigned priority,
-				enum radeon_bo_domain *added_domains)
+                                enum radeon_bo_domain rd,
+                                enum radeon_bo_domain wd,
+                                unsigned priority,
+                                enum radeon_bo_domain *added_domains)
 {
     *added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain);
 
@@ -434,33 +434,33 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
 
     switch (cs->base.ring_type) {
     case RING_DMA:
-	    /* pad DMA ring to 8 DWs */
-	    if (cs->ws->info.chip_class <= SI) {
-		    while (rcs->cdw & 7)
-			    OUT_CS(&cs->base, 0xf0000000); /* NOP packet */
-	    } else {
-		    while (rcs->cdw & 7)
-			    OUT_CS(&cs->base, 0x00000000); /* NOP packet */
-	    }
-	    break;
+        /* pad DMA ring to 8 DWs */
+        if (cs->ws->info.chip_class <= SI) {
+            while (rcs->cdw & 7)
+                OUT_CS(&cs->base, 0xf0000000); /* NOP packet */
+        } else {
+            while (rcs->cdw & 7)
+                OUT_CS(&cs->base, 0x00000000); /* NOP packet */
+        }
+        break;
     case RING_GFX:
-	    /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
-	     * r6xx, requires at least 4 dw alignment to avoid a hw bug.
-	     */
-	    if (cs->ws->info.chip_class <= SI) {
-		    while (rcs->cdw & 7)
-			    OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
-	    } else {
-		    while (rcs->cdw & 7)
-			    OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */
-	    }
-	    break;
+        /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
+         * r6xx, requires at least 4 dw alignment to avoid a hw bug.
+         */
+        if (cs->ws->info.chip_class <= SI) {
+            while (rcs->cdw & 7)
+                OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
+        } else {
+            while (rcs->cdw & 7)
+                OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */
+        }
+        break;
     case RING_UVD:
-            while (rcs->cdw & 15)
-		OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
-	    break;
+        while (rcs->cdw & 15)
+            OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
+        break;
     default:
-	    break;
+        break;
     }
 
     if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) {