From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 Jun 2018 05:37:17 +0000 (+0100)
Subject: add diagrams
X-Git-Tag: convert-csv-opcode-to-binary~5317
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd0bcce2c9c85e115965dd9065e85b5816bc8f5f;p=libreriscv.git

add diagrams
---

diff --git a/simple_v_extension/padd9_alu4.png b/simple_v_extension/padd9_alu4.png
new file mode 100644
index 000000000..bd57ae552
Binary files /dev/null and b/simple_v_extension/padd9_alu4.png differ
diff --git a/simple_v_extension/padd9_fifo.png b/simple_v_extension/padd9_fifo.png
new file mode 100644
index 000000000..81d924592
Binary files /dev/null and b/simple_v_extension/padd9_fifo.png differ
diff --git a/simple_v_extension/padd9_simd.png b/simple_v_extension/padd9_simd.png
new file mode 100644
index 000000000..46d0f0c72
Binary files /dev/null and b/simple_v_extension/padd9_simd.png differ
diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 9d28b1ebc..fc49acb64 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -170,6 +170,22 @@
 % but MODIFYING the remaining "vectorised" op, subtracting the now
 % scalar ops from it.
 
+\frame{\frametitle{Predicated 8-parallel ADD: optimised (not masked)}
+ \begin{center}
+  \includegraphics[height=2.5in]{padd9_alu4.png}\\
+  {\bf \red Predicated adds are shuffled down: 4 in 1st cycle, 2 in 2nd}
+ \end{center}
+}
+
+
+\frame{\frametitle{Predicated 8-parallel ADD: 3 phase FIFO expansion}
+ \begin{center}
+  \includegraphics[height=2.5in]{padd9_fifo.png}\\
+  {\bf \red First cycle takes first four 1s; second takes the rest}
+ \end{center}
+}
+
+
 \frame{\frametitle{How are SIMD Instructions Vectorised?}
 
  \begin{itemize}
@@ -189,6 +205,14 @@
 % or they can be used to cover several operations on totally different
 % vectors / registers.
 
+\frame{\frametitle{Predicated 9-parallel SIMD ADD}
+ \begin{center}
+  \includegraphics[height=2.5in]{padd9_simd.png}\\
+  {\bf \red 4-wide 8-bit SIMD, 4 bits of predicate passed to ALU}
+ \end{center}
+}
+
+
 \frame{\frametitle{What's the deal / juice / score?}
 
  \begin{itemize}