From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 8 Jul 2021 21:34:29 +0000 (+0100)
Subject: whoops asmcode length (number of instructions) went over 256, caused
X-Git-Tag: xlen-bcd~321
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd11c20dfef72426779d6b8b29231101eeab24fc;p=openpower-isa.git

whoops asmcode length (number of instructions) went over 256, caused
asmcode in simulator to "wrap" and get the wrong instruction name,
and then execute totally the wrong simulated instruction
---

diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py
index cd012f6f..1d480838 100644
--- a/src/openpower/decoder/decode2execute1.py
+++ b/src/openpower/decoder/decode2execute1.py
@@ -10,9 +10,11 @@ from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
 from openpower.consts import TT
 from openpower.exceptions import LDSTException
 from openpower.decoder.power_svp64_rm import sv_input_record_layout
+from openpower.decoder.power_enums import asmlen
 
 from openpower.util import log
 
+
 class Data(Record):
 
     def __init__(self, width, name):
@@ -102,7 +104,7 @@ class Decode2ToExecute1Type(RecordObject):
         RecordObject.__init__(self, name=name)
 
         if asmcode:
-            self.asmcode = Signal(8, reset_less=True) # only for simulator
+            self.asmcode = Signal(asmlen, reset_less=True) # only for simulator
         self.write_reg = Data(7, name="rego")
         self.write_ea = Data(7, name="ea") # for LD/ST in update mode
         self.read_reg1 = Data(7, name="reg1")
diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index 3bce7e84..024953a5 100644
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -96,7 +96,8 @@ from openpower.decoder.power_enums import (Function, Form, MicrOp,
                                      RC, LdstLen, LDSTMode, CryIn,
                                      single_bit_flags, CRInSel,
                                      CROutSel, get_signal_name,
-                                     default_values, insns, asmidx)
+                                     default_values, insns, asmidx,
+                                     asmlen)
 from openpower.decoder.power_fields import DecodeFields
 from openpower.decoder.power_fieldsn import SigDecode, SignalBitRange
 from openpower.decoder.power_svp64 import SVP64RM
@@ -120,7 +121,7 @@ Subdecoder = namedtuple(  # fix autoformatter
 power_op_types = {'function_unit': Function,
                   'internal_op': MicrOp,
                   'form': Form,
-                  'asmcode': 8,
+                  'asmcode': asmlen,
                   'SV_Etype': SVEtype,
                   'SV_Ptype': SVPtype,
                   'in1_sel': In1Sel,
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 67f81c3b..41d712e2 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -303,6 +303,9 @@ for i, insn in enumerate(_insns):
     insns[i] = insn
     asmidx[insn] = i
 
+# must be long enough to cover all instructions
+asmlen = len(_insns).bit_length()
+
 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)